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参数资料
| 型号： | 74ALVCH16601 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 |
| 中文描述： | 18位通用总线收发器，三态 |
| 文件页数： | 2/12页 |
| 文件大小： | 86K |
| 代理商： | 74ALVCH16601 |
Philips Semiconductors
Product specification
74ALVCH16601
18-bit universal bus transceiver (3-State)
2
1998 Sep 24
853-2122 20076
FEATURES
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
Current drive
±
24 mA at 3.0 V
All inputs have bus hold circuitry
Output drive capability 50
transmission lines @ 85
°
C
DESCRIPTION
The 74ALVCH16601 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
AB
and OE
BA
), latch enable (LE
AB
and LE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates
in the transparent mode when LE
AB
is High. When LE
AB
is Low, the
A data is latched if CP
AB
is held at a High or Low logic level. If LE
AB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
AB
. When OE
AB
is Low, the outputs are
active. When OE
AB
is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CE
BA
/CE
AB
).
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
.
To ensure the high impedance state during power up or power
down, OE
BA
and OE
AB
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
= 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An, Bn to Bn, An
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
3.1
2.8
ns
C
I/O
C
I
Input/Output capacitance
8.0
pF
Input capacitance
4.0
pF
C
PD
Power dissipation capacitance per latch
V = GND to V
CC1
Outputs enabled
21
pF
Outputs disabled
3
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
= C
×
V
CC2
×
f
+ (C
L
×
V
CC2
×
f
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74ALVCH16601 DGG
DWG NUMBER
SOT364-1
相关PDF资料 |
PDF描述 |
|---|---|
| 74ALVCH16623DGG | 16-bit transceiver with dual enable; 3-state |
| 74ALVCH16623 | 16-bit transceiver with dual enable; 3-state |
| 74ALVCH16646 | Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 |
| 74ALVCH16652 | 16-bit transceiver/register with dual enable; 3-state |
| 74ALVCH16821 | Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 74ALVCH16601DG | 功能描述:总线收发器 18-BIT UNIV BUS XCVR 3-STATE RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74ALVCH16601DGG | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:18-bit universal bus transceiver 3-State |
| 74ALVCH16601DGG,11 | 功能描述:总线收发器 18-BIT UNIV BUS RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74ALVCH16601DGG,112 | 制造商:NXP Semiconductors 功能描述: |
| 74ALVCH16601DGG,118 | 制造商:NXP Semiconductors 功能描述: |
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