参数资料
型号: 74ALVCH16652
厂商: NXP Semiconductors N.V.
英文描述: 16-bit transceiver/register with dual enable; 3-state
中文描述: 16位收发器/寄存器双使,三态
文件页数: 10/20页
文件大小: 103K
代理商: 74ALVCH16652
1999 Nov 23
10
Philips Semiconductors
Product specification
16-bit transceiver/register with dual enable; 3-state
74ALVCH16652
AC CHARACTERISTICS FOR V
CC
= 2.3 TO 2.7 V
Ground = 0 V; t
r
= t
f
2.0 ns; C
L
= 30 pF.
Note
1.
All typical values are measured at T
amb
= 25
°
C and V
CC
= 2.5 V.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
=
40 TO +85
°
C
UNIT
WAVEFORMS
V
CC
(V)
2.3 to 2.7
MIN.
TYP.
(1)
MAX.
t
PHL
/t
PLH
propagation delay
nA
n
, nB
n
to nB
n
, nA
n
propagation delay
nCP
AB
, nCP
BA
to nB
n
, nA
n
propagation delay
nS
AB
, nS
BA
to nB
n
, nA
n
3-state output enable time
nOE
AB
to nB
n
3-state output disable time
nOE
AB
to nB
n
3-state output enable time
nOE
BA
to nA
n
3-state output disable time
nOE
BA
to nA
n
clock pulse width HIGH or
LOW nCP
AB
or nCP
BA
set-up time
nA
n
, nB
n
to nCP
AB
, nCP
BA
hold time
nA
n
, nB
n
to nCP
AB
, nCP
BA
maximum clock pulse
frequency
see Figs 6 and 10
1.0
2.7
4.8
ns
see Figs 8 and 10
2.3 to 2.7
1.0
3.4
6.8
ns
see Figs 7 and 10
2.3 to 2.7
1.0
3.4
5.6
ns
t
PZH
/t
PZL
see Figs 9 and 10
2.3 to 2.7
1.0
2.6
4.5
ns
t
PHZ
/t
PLZ
see Figs 9 and 10
2.3 to 2.7
1.6
2.7
4.5
ns
t
PZH
/t
PZL
see Figs 9 and 10
2.3 to 2.7
3.3
2.8
4.5
ns
t
PHZ
/t
PLZ
see Figs 9 and 10
2.3 to 2.7
3.3
2.5
4.5
ns
t
W
see Figs 8 and 10
2.3 to 2.7
2.2
1.2
ns
t
su
see Figs 8 and 10
2.3 to 2.7
2.2
0.2
ns
t
h
see Figs 8 and 10
2.3 to 2.7
0.6
0.1
ns
f
max
see Figs 8 and 10
2.3 to 2.7
150
300
MHz
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