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参数资料
| 型号： | 74ALVCH16821 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 |
| 中文描述： | 20位总线接口D型触发器;积极边缘触发三态 |
| 文件页数： | 2/12页 |
| 文件大小： | 95K |
| 代理商： | 74ALVCH16821 |
Philips Semiconductors
Product specification
74ALVCH16821
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2
1998 May 29
853-2066 19467
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Current drive
±
24 mA at 3.0 V
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
All data inputs have bus hold
Output drive capability 50
transmission lines @ 85
°
C
DESCRIPTION
The 74ALVCH16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16821 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nCP to nQ
n
Input capacitance
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.6
2.5
ns
C
I
5.0
pF
C
PD
Power dissipation capacitance per buffer
V = GND to V
CC1
Outputs enabled
33
pF
Outputs disabled
17
F
max
Maximum clock frequency
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
250
350
MHz
NOTE:
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ALVCH16821 DL
ACH16821 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ALVCH16821 DGG
ACH16821 DGG
SOT364-1
相关PDF资料 |
PDF描述 |
|---|---|
| 74ALVCH16823 | Automotive Catalog Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 125 |
| 74ALVCH16825 | Automotive Catalog Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 125 |
| 74ALVCH16827 | 20-bit buffer/line driver, non-inverting 3-State |
| 74ALVCH16841DL | 20-bit bus interface D-type latch (3-State) |
| 74ALVCH16841 | 20-bit bus interface D-type latch 3-State |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 74ALVCH16821DG | 功能描述:触发器 20-BIT BUS INTERFACE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| 74ALVCH16821DGG | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State |
| 74ALVCH16821DGG,11 | 功能描述:触发器 20-BIT BUS INTERFACE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| 74ALVCH16821DGG,112 | 制造商:NXP Semiconductors 功能描述: |
| 74ALVCH16821DGG,118 | 制造商:NXP Semiconductors 功能描述: |
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