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参数资料
| 型号： | 74HC4059N,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC PROG DIV-BY-N COUNTER 24-DIP |
| 产品培训模块： | Logic Packages |
| 标准包装： | 360 |
| 系列： | 74HC |
| 逻辑类型： | 除以 N |
| 方向： | 下 |
| 元件数： | 1 |
| 每个元件的位元数： | 16 |
| 复位： | 异步 |
| 计时： | 同步 |
| 计数速率： | 43MHz |
| 触发器类型： | 正边沿 |
| 电源电压： | 2 V ~ 6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 24-DIP |
| 包装： | 管件 |
1998 Jul 08
12
Philips Semiconductors
Product specication
Programmable divide-by-n counter
74HC/HCT4059
APPLICATION INFORMATION
Fig.10 Example showing the application of the PC74HC/HCT4059 in a phase-locked-loop (PLL) for a FM band
synthesizer.
Calculating the minimum and maximum divide-by-n
values:
Output frequency range = 87.6 to 103.8 MHz
(CCIR band 2)
Channel spacing frequency (fc) = 300 kHz
Division factor prescaler (k) = 10
Reference frequency (fr) =
Maximum divide-by-n value =
Minimum divide-by-n value =
Fixed divide-by-n value =
Application of the “4059” as divide-by-n counter allows
programming of the channel spacing (shown in equations
as 300 kHz). A channel in the CCIR band 2 is selected by
the divide-by-n counter as follows:
channel = n
290
f
c
k
----
300
10
----------
30 kHz
==
103.8 MHz
300 kHz
-----------------------------
346
=
87.6 MHz
300 kHz
-------------------------
292
=
3MHz
30 kHz
------------------
100
=
Figure 11 shows a BCD switch compatible arrangement
suitable for divide-by-5 and divide-by-8 modes, which can
be adapted (with minimal changes) to the other
divide-by-modes. In order to be able to preset to any
number from 3 to 256 000, while preserving the BCD
switch compatible character of the JAM inputs, a rather
complex cascading scheme is necessary because the
“4059” can never be preset to count less than 3. Logic
circuitry is required to detect a condition where one of the
numbers to be preset in the “4059” is
< 3. In order to
simplify the detection logic, only that condition is detected
where the JAM inputs to terminals 6, 7 and 9 would be
LOW during one count. If such a condition is detected, and
if at least 1 is expected to be jammed into the MSB
counter, the detection logic removes one from the number
to be jammed into the MSB counter (with a place value of
2 000 times the divide-by-mode) and jams the same 2 000
into the “4059” by forcing pins 6, 7 and 9 HIGH.
The general circuit in Fig.11 can be simplified considerably
if the range of the cascaded counters do not start at a very
low value.
Figure 12 shows an arrangement in the divide-by-4 mode,
where the counting range extends in a BCD switch
compatible manner from 99 003 to 114 999.
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