参数资料
型号: 74HC7046APW
厂商: NXP SEMICONDUCTORS
元件分类: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, PDSO16
封装: PLASTIC, TSSOP
文件页数: 20/38页
文件大小: 468K
代理商: 74HC7046APW
December 1990
27
Philips Semiconductors
Product specication
Phase-locked-loop with lock detector
74HC/HCT7046A
APPLICATION INFORMATION
This information is a guide for the approximation of values of external components to be used with the 74HC/HCT7046
in a phase-lock-loop system.
References should be made to Figs 27, 28 and 29 as indicated in the table.
Values of the selected components should be within the following ranges:
R1
between 3 k
and 300 k;
R2
between 3 k
and 300 k;
R1
+ R2 parallel value > 2.7 k;
C1
greater than 40 pF.
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
VCO frequency characteristic
VCO frequency
without extra
offset
PC1, PC2
With R2 =
∞ and R1 within the range 3 k< R1 < 300 k, the characteristics
of the VCO operation will be as shown in Fig. 23.
(Due to R1, C1 time constant a small offset remains when R2 =
∞.)
Fig. 23 Frequency characteristic of VCO operating without offset:
fo = centre frequency; 2fL = frequency lock range.
Selection of R1 and C1
PC1
Given fo, determine the values of R1 and C1 using Fig.27.
PC2
Given fmax and fo, determine the values of R1 and C1 using Fig.27,
use Fig.29 to obtain 2fL and then use this to calculate fmin.
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