参数资料
型号: 74LV74PW,112
厂商: NXP Semiconductors
文件页数: 19/19页
文件大小: 0K
描述: IC DUAL D FF POSEDG TRIG 14TSSOP
产品培训模块: Logic Packages
标准包装: 2,400
系列: 74LV
功能: 设置(预设)和复位
类型: D 型
输出类型: 差分
元件数: 2
每个元件的位元数: 1
频率 - 时钟: 56MHz
触发器类型: 正边沿
输出电流高,低: 12mA,12mA
电源电压: 1 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
包装: 管件
74LV74
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 9 September 2013
9 of 19
NXP Semiconductors
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
[1]
Typical values are measured at Tamb = 25 °C.
[2]
tpd is the same as tPHL and tPLH.
[3]
Typical value measured at VCC = 3.3 V.
[4]
Typical values are measured at VCC = 5.0 V.
[5]
CPD is used to determine the dynamic power dissipation PD = CPD VCC2 fi + (CL VCC2 fo) (PD in W), where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(C
L VCC
2
f
o) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
trec
recovery time
nRD; see Figure 7
VCC = 1.2 V
-
5
-
ns
VCC = 2.0 V
14
2
-
15
-
ns
VCC = 2.7 V
10
1
-
11
-
ns
VCC = 3.0 V to 3.6 V
81
-
9
-
ns
VCC = 4.5 V to 5.5 V
61
-
7
-
ns
tsu
set-up time
nD to nCP; see Figure 6
VCC = 1.2 V
-
10
-
ns
VCC = 2.0 V
22
4
-
26
-
ns
VCC = 2.7 V
12
3
-
15
-
ns
VCC = 3.0 V to 3.6 V
82
-
10
-
ns
VCC = 4.5 V to 5.5 V
61
-
8
-
ns
th
hold time
nD to nCP; see Figure 6
VCC = 1.2 V
-
10
-
ns
VCC = 2.0 V
3
2-
3
-
ns
VCC = 2.7 V
3
2-
3
-
ns
VCC = 3.0 V to 3.6 V
3
2-
3
-
ns
VCC = 4.5 V to 5.5 V
3
2-
3
-
ns
fmax
maximum
frequency
nCP; see Figure 6
VCC = 2.0 V
14
40
-
12
-
MHz
VCC = 2.7 V
50
90
-
40
-
MHz
VCC = 3.0 V to 3.6 V
60
100
-
48
-
MHz
VCC = 4.5 V to 5.5 V
70
110
-
56
-
MHz
CPD
power
dissipation
capacitance
VI =GND to VCC
-24
-
pF
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V): for test circuit, see Figure 8
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
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