参数资料
型号: 7805ALPRPFS
厂商: MAXWELL TECHNOLOGIES
元件分类: ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28
封装: RAD-PAK, LDFP-28
文件页数: 16/34页
文件大小: 605K
代理商: 7805ALPRPFS
Memory
PRELIMINARY
23
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
LDAC FUNCTION
LDAC input is a logic input that allows all DAC registers to be simultaneously updated with the contents of the DAC
data registers. LDAC input has two operating modes, a synchronous mode and an asynchronous mode. The LDAC
input condition is sampled on the rising edge of write. If LDAC is low on the sixteenth falling clock edge or on the rising
edge of WR, an automatic or synchronous update will take place. LDAC input can be tied permanently low or have
timing similar to that of the data inputs to operate in the synchronous mode.
If LDAC is high during the sample period, the 7805ALPassumes an asynchronous update. When in the asynchronous
mode, an LDAC setup time has to be allowed following the sixteenth falling clock edge or the rising edge of WR before
the LDAC can be activated.
ANALOG OUTPUTS
The 7805ALP’s DAC contains four independent voltage output Main DACs with 10-bit resolution. Each Main DAC has
an associated Sub DAC with 8-bit resolution which can be used to offset the complete transfer function of the Main
DAC around the VBIAS point. These DACs produce an output voltage in the form of VBIAS ±VSWING where
VSWING is 15/16 of VBIAS.
The digital input code to these DACs can be in twos complement or offset binary form. All DACs will be configured with
the same input coding scheme which is programmed through the system control register. The default condition on
power-up is for offset binary coding.
TWOS COMPLEMENT CODING
Table 20 shows the twos complement transfer function for the Main DAC.
TABLE 20. TWOS COMPLEMENT CODE TABLE FOR MAIN DAC DIGITAL INPUT ANALOG OUTPUT
相关PDF资料
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7805ALPRPDS 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28
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