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参数资料
| 型号： | 78M6610+PSU/C00 |
| 厂商： | Maxim Integrated |
| 文件页数： | 50/63页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY MEASURMENT 1PH 16TSSOP |
| 标准包装： | 96 |
| 输入阻抗： | 30 千欧 ~ 90 千欧 |
| 电压 - 高输入/输出： | 2V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 8.1mA |
| 电源电压： | 3 V ~ 3.6 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
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78M6610+PSU Data Sheet
Bus Characteristics
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A data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Bus Conditions:
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Bus not Busy (I): Both data and clock lines are HIGH indicating an Idle Condition.
Start Data Transfer (S): a HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH
determines a START condition. All commands must be preceded by a START condition.
Stop Data Transfer (P): a LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH
determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid: The state of the data line represents valid data when, after a START condition, the data
line is stable for the duration of the HIGH period of the clock signal. The data on the line must be
changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each
data transfer is initiated with a START condition and terminated with a STOP condition.
Acknowledge (A): Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse, which is
associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH
period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into
account. During reads, a master must signal an end of data to the slave by not generating an
Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave
(78M6610+PSU) will leave the data line HIGH to enable the master to generate the STOP condition.
SDA
MSB
SCL
1
2
7
8
9
ACK
9
ACK
Start Bit
SCL may be held low by
slave to service interrupts
Start or Stop Bits
Device Addressing
A control byte is the first byte received following the START condition from the master device.
The control byte consists of a seven bit address and a bit (LSB) indicating the type of access (0=write;
1=read).
DEVICE ADDRESS
LSB
MSB
S
X
X
X
X
X
X
X
R/W ACK
START BIT
50
READ/WRITE
ACKNOWLEDGE
Rev 1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 78M6611-EVM | 制造商:Maxim Integrated Products 功能描述:78M6611 EVAL BOARD - Boxed Product (Development Kits) |
| 78M6611-IVT/F | 功能描述:IC POWER MEASUREMENT AC 24-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| 78M6611-IVT/F/P | 制造商:Maxim Integrated Products 功能描述:PROGRAMMED - LEAD FREE - Rail/Tube |
| 78M6611-IVTR/F | 功能描述:IC POWER MEASUREMENT AC 24-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
| 78M6611-IVTR/F/P | 制造商:Maxim Integrated Products 功能描述:PROGRAMMED - LEAD FREE/TAPE & REEL - Tape and Reel |
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