参数资料
型号: 78P2351R-IMR/F
厂商: Maxim Integrated Products
文件页数: 29/31页
文件大小: 0K
描述: IC LIU NRZ-CMI CONV 155M 56-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: E4,OC-3,STM1-E
电源电压: 3.15 V ~ 3.45 V
安装类型: 表面贴装
封装/外壳: 56-VFQFN 裸露焊盘
供应商设备封装: 56-QFN-EP(7x7)
包装: 带卷 (TR)
78P2351R
Serial 155M
NRZ to CMI Converter
Page: 7 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
INTERNAL POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Roughly 50
s after Vcc reaches 2.4V at power up,
a reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin.
The PORB pin is a special function
analog pin that allows for the following:
Override the internal POR signal by driving in
an external active low reset signal;
Use the internally generated POR signal to
trigger other resets;
Add external capacitor to slow down the
release of power-on reset (approximately 8
s
per nF added).
NOTE: Do not pull-up the PORB pin to Vcc or drive
this pin high during power-up. This will prevent the
internal reset generator from resetting the entire chip
and may result in errors.
SERIAL CONTROL INTERFACE
The serial port controlled register allows a generic
controller to interface with the 78P2351R. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
fuse trimming during production test. The SPSL pin
must be high in order to use the serial port.
The serial interface consists of 4 pins:
Serial Port Enable (SEN),
Serial Clock (SCK_MON),
Serial Data In (SDI),
Serial Data Out (SDO).
The SEN pin initiates the read and write operations.
It can also be used to select a particular device
allowing SCK_MON, SDI and SDO to be bussed
together.
SCK_MON is the clock input that times the data on
SDI and SDO. Data on SDI is latched in on the
rising-edge of SCK_MON, and data on SDO is
clocked out using the falling edge of SCK_MON.
SDI is used to insert mode, address, and register
data into the chip. Address and Data information
are input least significant bit (LSB) first. The mode
and address bit assignment and register table are
shown in the following section.
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only during
the duration when register data is being clocked out.
Read data is clocked out least significant bit (LSB)
first.
If SDI coming out of the micro-controller chip is also
tristate capable, SDI and SDO can be connected
together to simplify connections.
The maximum clock frequency for register access is
20MHz.
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