859S0424AGILF PDF资料下载(16/18 页)859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVE

您好，
买卖IC网欢迎您。
请登录
免费注册

您现在的位置：买卖IC网 > PDF目录163355 > 859S0424AGILF (INTEGRATED DEVICE TECHNOLOGY INC) 859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 PDF资料下载

参数资料

型号：	859S0424AGILF
厂商：	INTEGRATED DEVICE TECHNOLOGY INC
元件分类：	时钟及定时
英文描述：	859S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封装：	4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
文件页数：	16/18页
文件大小：	1530K
代理商：	859S0424AGILF

第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页

ICS859S0424I

4:4, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER

PRELIMINARY

IDT / ICS LVPECL/LVDS CLOCK MULTIPLEXER

ICS859S0424AGI REV. A MAY 18, 2007

Table 6C. LVDS AC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.

Using the same type of input on each device, the output is measured at the differential cross points.

Table 6D. LVDS AC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, TA = -40°C to 85°C

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.

Using the same type of input on each device, the output is measured at the differential cross points.

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

3GHz

tPD

Propagation Delay; NOTE 1

550

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

100MHz, Integration Range:

12kHz – 20MHz

0.28

tsk(b)

Bank Skew; NOTE 2, 3

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

TBD

tR / tF

Output Rise/Fall Time

20% to 80%

220

odc

Output Duty Cycle

MUXISOLATION MUX Isolation

OUT < 1.2GHz