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参数资料
| 型号： | 89C52 |
| 厂商： | Integrated Silicon Solution, Inc. |
| 英文描述： | CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 8-Kbytes of FLASH |
| 中文描述： | CMOS单芯片的8位单片机，带有8的快闪记忆体 |
| 文件页数： | 11/50页 |
| 文件大小： | 425K |
| 代理商： | 89C52 |
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IS89C52
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC013-1C
11/21/98
11
ISSI
The detail description of each bit is as follows:
PSW:
Program Status Word. Bit Addressable.
7
6
5
4
3
2
1
—
0
P
CY
AC
F0
RS1
RS0
OV
Register Description:
CY
PSW.7
AC
PSW.6
F0
PSW.5
Carry flag.
Auxiliary carry flag.
Flag 0 available to the user for general
purpose.
Register bank selector bit 1.
(1)
Register bank selector bit 0.
(1)
Overflow flag.
Usable as a general purpose flag
Parity flag. Set/Clear by hardware each
instruction cycle to indicate an odd/even
number of “1” bits in the accumulator.
RS1
RS0
OV
—
P
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0
Note:
1. The value presented by RS0 and RS1 selects the corre-
sponding register bank.
RS1
0
0
1
1
RS0
0
1
0
1
Register Bank
0
1
2
3
Address
00H-07H
08H-0FH
10H-17H
18H-1FH
PCON:
Power Control Register. Not Bit Addressable.
7
6
—
5
4
—
3
2
1
0
SMOD
—
GF1
GF0
PD
IDL
Register
SMOD
Description:
Double baud rate bit. If Timer 1 is used to generate
baud rate and SMOD=1, the baud rate is doubled
when the serial port is used in modes 1, 2, or 3.
Not implemented, reserve for future use.
(1)
Not implemented, reserve for future use.
(1)
Not implemented, reserve for future use.
(1)
General purpose flag bit.
General purpose flag bit.
Power-down bit. Setting this bit activates power-
down mode.
Idle mode bit. Setting this bit activates idle mode.
If 1s are written to PD and IDL at the same time,
PD takes precedence.
—
—
—
GF1
GF0
PD
IDL
Note:
1. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
IE:
Interrupt Enable Register. Bit Addressable.
7
6
—
5
—
4
3
2
1
0
EA
ES
ET1
EX1
ET0 EX0
Register Description:
EA
IE.7
Disable all interrupts. If EA=0, no
interrupt will be acknowledged. If EA=1,
each interrupt source is individually
enabled or disabled by setting or
clearing its enable bit.
Not implemented, reserve for future
use.
(5)
Not implemented, reserve for future
use.
(5)
Enable or disable the serial port
interrupt.
Enable or disable the Timer 1 overflow
interrupt.
Enable or disable External Interrupt 1.
Enable or disable the Timer 0 overflow
interrupt.
Enable or disable External Interrupt 0.
—
IE.6
—
IE.5
ES
IE.4
ET1
IE.3
EX1
ET0
IE.2
IE.1
EX0
IE.0
Note:
To use any of the interrupts in the 80C51 Family, the
following three steps must be taken:
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the coresponding individual interrupt enable bit in
the IE register to 1.
3. Begin the interrupt service routine at the corresponding
Vector Address of that interrupt (see below).
Interrupt Source
IE0
TF0
IE1
TF1
RI & TI
Vector Address
0003H
000BH
0013H
001BH
0023H
4. In addition, for external interrupts, pins
INT0
and
INT1
(P3.2 and P3.3) must be set to 1, and depending on
whether the interrupt is to be level or transition acti-
vated, bits IT0 or IT1 in the TCON register may need to
be set to 0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5.
User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new
features.
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