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April 11, 2007
2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
DSC 6929
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Inc.
Devic e Overview
The 89HPES12NT3 is a member of the IDT PRECISE famly of
PCI Expressswitching solutions offering the next-generation I/O inter-
connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip
that performs PCI Express Base switching with a feature set optimzed
for high performance applications such as servers, storage, and commu-
nications/networking. It provides high-performance I/O connectivity and
switching functions between a PCIeupstreamport, a transparent
downstreamport, and a non-transparent downstreamport.
With non-transparent bridging (NTB) functionality, the PES12NT3
can be used standalone or as a chipset with IDT PCIe SystemIntercon-
nect Switches in multi-host and intelligent I/O applications such as
communications, storage, and blade servers where inter-domain
communication is required.
Features
◆
High Performance PCI Express Switch
–
Twelve PCI Express lanes (2.5Gbps), three switch ports
–
Delivers 48 Gbps (6 GBps) of aggregate switching capacity
–
Low latency cut-through switch architecture
–
Support for Max Payload size up to 2048 bytes
–
Supports one virtual channel and eight traffic classes
–
PCI Express Base specification Revision 1.0a compliant
◆
Flexible Architecture with Numerous Configuration Options
–
Port arbitration schemes utilizing round robin
–
Supports automatic per port link width negotiation (x4, x2, or
x1)
–
Static lane reversal on all ports
–
Automatic polarity inversion on all lanes
–
Supports locked transactions, allowing use with legacy soft-
ware
–
Ability to load device configuration fromserial EEPROM
–
Ability to control device via SMBus
◆
Non-Transparent Port
–
Crosslink support on NTB port
–
Four mapping windows supported
Each may be configured as a 32-bit memory or I/O window
May be paired to forma 64-bit memory window
–
Interprocessor communication
Thirty-two inbound and outbound doorbells
Four inbound and outbound message registers
Two shared scratchpad registers
–
Allows up to sixteen masters to communicate through the non-
transparent port
–
No limt on the number of supported outstanding transactions
through the non-transparent bridge
–
Completely symmetric non-transparent bridge operation
allows simlar/same configuration software to be run
–
Supports direct connection to a transparent or non-transparent
port of another switch
Block Diagram
Figure 1 Internal Block Diagram
12 PCI Express Lanes
x4 Upstream Port and Two x4 Downstream Ports
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
3-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Non-
Transparent
Bridge
89HPES12NT3
Data Sheet
Preliminary Information*
12-lane 3-Port Non-Transparent
PCI Express Switch