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参数资料
| 型号： | 89HPES12NT3 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 中文描述： | 12通道三端口非透明的PCI Express㈢开关 |
| 文件页数： | 12/29页 |
| 文件大小： | 263K |
| 代理商： | 89HPES12NT3 |
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12 of 29
April 11, 2007
IDT 89HPES12NT3 Data Sheet
T
RX-EYE-MEDIUMTO
MAX JITTER
Max time between jitter median & max deviation
0.3
UI
T
RX-IDLE-DET-DIFF-
ENTER TIME
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
T
RX-SKEW
Lane to lane input skew
20
ns
1.
Minimum Typical, and Maximumvalues meet the requirements under PCI Specification 1.0a
S ignal
S ymbol
Referenc e
Edge
Min
Max Unit
T iming
Diagram
Referenc e
GPIO
GPIO[7:0]
1
1.
GPIO signals must meet the setup and hold times if they are synchronous or the mnimumpulse width if
they are asynchronous.
2.
The values for this symbol were determned by calculation, not by testing.
Tpw_13b
2
None
50
—
ns
Table 10 GPIO AC Timing Characteristics
S ignal
S ymbol
Referenc e
Edge
Min
Max
Unit
T iming
Diagram
Referenc e
JTAG
JTAG_TCK
Tper_16a
none
50.0
—
ns
See Figure 5.
Thigh_16a,
Tlow_16a
10.0
25.0
ns
JTAG_TMS
1
,
JTAG_TDI
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going fromlow to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller mght go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determned by calculation, not by testing.
Tsu_16b
JTAG_TCK rising
2.4
—
ns
Thld_16b
1.0
—
ns
JTAG_TDO
Tdo_16c
JTAG_TCK falling
—
20
ns
Tdz_16c
2
—
20
ns
JTAG_TRST_N
Tpw_16d
2
none
25.0
—
ns
Table 11 JTAG AC Timing Characteristics
Parameter
Desc ription
Min
1
Typical
1
Max
1
Units
Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
相关PDF资料 |
PDF描述 |
|---|---|
| 89HPES12NT3ZABC | 12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12NT3ZABCG | 12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12T3G2 | 12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES12T3G2ZABC | 12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES12T3G2ZABCG | 12-Lane 3-Port Gen2 PCI Express Switch |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 89HPES12NT3ZABC | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12NT3ZABCG | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12NT3ZBBC | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:托盘 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:84 |
| 89HPES12NT3ZBBC8 | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:带卷（TR） 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:750 |
| 89HPES12NT3ZBBCG | 功能描述:接口-I/O扩展器 RoHS:否 制造商:NXP Semiconductors 逻辑系列: 输入/输出端数量: 最大工作频率:100 kHz 工作电源电压:1.65 V to 5.5 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:HVQFN-16 封装:Reel |
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