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参数资料
| 型号： | 89HPES12NT3 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 中文描述： | 12通道三端口非透明的PCI Express㈢开关 |
| 文件页数： | 2/29页 |
| 文件大小： | 263K |
| 代理商： | 89HPES12NT3 |
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April 11, 2007
IDT 89HPES12NT3 Data Sheet
*Notice: The information in this document is subject to change without notice
◆
Highly Integrated Solution
–
Requires no external components
–
Incorporates on-chip internal memory for packet buffering and
queueing
–
Integrates twelve 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
–
Upstreamport can be dynamcally swapped with non-trans-
parent downstreamport to support failover applications
–
Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
–
Supports ECRC pass-through in transparent and non-trans-
parent ports
–
Supports Hot-Swap
◆
Power Management
–
Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
–
Unused SerDes are disabled
◆
Testability and Debug Features
–
Built in SerDes Pseudo-RandomBit Stream(PRBS) generator
–
Ability to read and write any internal register via the SMBus
–
Ability to bypass link training and force any link into any mode
–
Provides statistics and performance counters
◆
Two SMBus Interfaces
–
Slave interface provides full access to all software-visible
registers by an external SMBus master
–
Master interface provides connection for an optional serial
EEPROMused for initialization
–
Master interface is also used by an external Hot-Plug I/O
expander
–
Master and slave interfaces may be tied together so the switch
can act as both master and slave
◆
Eight General Purpose Input/Output pins
◆
Packaged in 19x19mm 324-ball BGA with 1mm ball spacing
Produc t Desc ription
Utilizing standard PCI Express interconnect, the PES12NT3 provides
the most efficient high-performance I/O connectivity solution for applica-
tions requiring high throughput, low latency, and simple board layout
with a mnimumnumber of board layers. With support for non-trans-
parent bridging, the PES12NT3, as a standalone switch or as a chipset
with IDT PCIe SystemInterconnect Switches, enables multi-host and
intelligent I/O applications requiring inter-domain communication. The
PES12NT3 provides 48 Gbps (6 GBps) of aggregated, full-duplex
switching capacity through 12 integrated serial lanes, using proven and
robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in
both directions and is fully compliant with PCI Express Base specifica-
tion 1.0a.
The PES12NT3 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES12NT3 can operate either as a store and
forward or cut-through switch depending on the packet size and is
designed to switch memory and I/O transactions. It supports eight Traffic
Classes (TCs) and one Virtual Channel (VC) with sophisticated resource
management. This includes round robin port arbitration, guaranteeing
bandwidth allocation and/or latency for critical traffic classes in applica-
tions such as high throughput 10 GbE I/Os, SATA controllers, and Fibre
Channel HBAs.
S w itch Configuration
The PES12NT3 is a three port switch that contains 12 PCI Express
lanes. Each of the three ports is statically allocated 4 lanes with ports
labeled as A, B and C. Port A is the upstreamport, port B is the trans-
parent downstreamport, and port C is the non-transparent downstream
port.
During link training, link width is automatically negotiated. Each
PES12NT3 port is capable of independently negotiating to a x4, x2 or x1
width. Thus, the PES12NT3 may be used in virtually any three port
switch configuration (e.g., {x4, x4, x4}, {x4, x2, x2}, {x4, x2, x1}, etc.).
The PES12NT3 supports static lane reversal. For example, lane
reversal for upstreamport A may be configured by asserting the PCI
Express Port A Lane Reverse (PEALREV) input signal or through serial
EEPROMor SMBus initialization. Lane reversal for ports B and C may
be enabled via a configuration space register, serial EEPROM or the
SMBus.
相关PDF资料 |
PDF描述 |
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| 89HPES12NT3ZABC | 12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12NT3ZABCG | 12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12T3G2 | 12-Lane 3-Port Gen2 PCI Express Switch |
| 89HPES12T3G2ZABC | 12-Lane 3-Port Gen2 PCI Express Switch |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 89HPES12NT3ZABC | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12NT3ZABCG | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:12-lane 3-Port Non-Transparent PCI Express㈢ Switch |
| 89HPES12NT3ZBBC | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:托盘 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:84 |
| 89HPES12NT3ZBBC8 | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:带卷（TR） 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:750 |
| 89HPES12NT3ZBBCG | 功能描述:接口-I/O扩展器 RoHS:否 制造商:NXP Semiconductors 逻辑系列: 输入/输出端数量: 最大工作频率:100 kHz 工作电源电压:1.65 V to 5.5 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:HVQFN-16 封装:Reel |
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