参数资料
型号: 89HPES12NT3ZABCG
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线控制器
英文描述: 12-lane 3-Port Non-Transparent PCI Express㈢ Switch
中文描述: PCI BUS CONTROLLER, PBGA324
封装: 19 X 19 MM, 1 MM PITCH, GREEN, BGA-324
文件页数: 14/29页
文件大小: 263K
代理商: 89HPES12NT3ZABCG
14 of 29
April 11, 2007
IDT 89HPES12NT3 Data Sheet
Power-Up S equenc e
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES12NT3, the power-up sequence must be as follows:
1. V
DD
I/O — 3.3V
2. V
DD
Core, V
DD
PE, V
DD
APE — 1.0V
3. V
TT
PE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximumtime limtations in ramping to valid power levels. The power-down sequence must be in the reverse order of the
power-up sequence.
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14.
Maximumpower is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximumvoltages defined in
Table 14.
All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFMairflow
Number of
Connec ted Lanes:
Port-A/Port-B/Port-C
Core (Watts)
(1.0V supply)
PCIe Digital
(Watts)
(1.0V supply)
PCIe Analog
(Watts)
(1.0V supply)
PCIe Termin-
ation (Watts)
(1.5V supply)
I/O (Watts)
(3.3V supply)
Total (Watts)
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
1/1/1
0.52
0.67
0.27
0.36
0.13
0.16
0.11
0.13
0.01
0.01
1.04
1.33
4/1/1
0.56
0.76
0.47
0.58
0.19
0.21
0.22
0.26
0.01
0.01
1.44
1.81
4/4/4
0.65
0.89
0.68
0.81
0.21
0.25
0.38
0.51
0.01
0.01
1.92
2.47
Table 14 PES12NT3 Power Consumption
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