参数资料
型号: 89HPES12T3G2ZABC
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线控制器
英文描述: 12-Lane 3-Port Gen2 PCI Express Switch
中文描述: PCI BUS CONTROLLER, PBGA324
封装: 19 X 19 MM, 1 MM PITCH, CABGA-324
文件页数: 12/31页
文件大小: 291K
代理商: 89HPES12T3G2ZABC
12 of 31
September 4, 2007
IDT 89HPES12T3G2 Data Sheet
A
T
TX-IDLE-SET-TO-
IDLE
Maximumtime to transition to a valid Idle after sending
an Idle ordered set
8
8
ns
T
TX-IDLE-TO-DIFF-
DATA
Maximumtime to transition fromvalid idle to diff data
8
8
ns
T
TX-SKEW
Transmtter data skew between any 2 lanes
1.3
1.3
ns
T
MIN-PULSED
MnimumInstantaneous Lone Pulse Width
NA
0.9
UI
T
MEAS-HPF
Transmt Jitter Measurement Filter
HPF: 1.5MHz
HPF: 1.0MHz
MHz
T
TX-HF-DJ-DD
Transmtter Determnistic Jitter > 1.5MHz Bandwidth
NA
0.15
UI
T
RF-MISMATCH
Rise/Fall Time Differential Msmatch
NA
0.1
UI
PCIe Receive
UI
Unit Interval
399.88
400
400.12
199.94
200.06
ps
T
RX-EYE (with jitter)
MnimumReceiver Eye Width (jitter tolerance)
0.4
0.4
UI
T
RX-EYE-MEDIUMTO
MAX JITTER
Max time between jitter median & max deviation
0.3
UI
T
RX-SKEW
Lane to lane input skew
20
8
ns
T
RX-HF-RMS
1.5 — 100 MHz RMS jitter
NA
4.2
ps
T
RX-HF-DJ-DD
Maximumtolerable DJ by the receiver
NA
8.8
ps
T
RX-LF-RMS
10 KHz to 1.5 MHz RMS jitter
NA
4.2
ps
T
RX-MIN-PULSE
Mnimumreceiver instantaneous eye width
NA
0.6
UI
1.
Minimum Typical, and Maximumvalues meet the requirements under PCI Specification 2.0
S ignal
S ymbol
Referenc e
Edge
Min
Max Unit
T iming
Diagram
Referenc e
GPIO
GPIO[15:0]
1
1.
GPIO signals must meet the setup and hold times if they are synchronous or the mnimumpulse width if
they are asynchronous.
2.
The values for this symbol were determned by calculation, not by testing.
Tpw
2
None
50
ns
Table 11 GPIO AC Timing Characteristics
Parameter
Desc ription
Gen 1
Gen 2
Units
Min
1
Typ
1
Max
1
Min
1
Typ
1
Max
1
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
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