- 您现在的位置：买卖IC网 > PDF目录9508 > 8N3QV01EG-0011CDI8 (IDT, Integrated Device Technology Inc)IC VCXO LVPECL QD FREQUENCY 5X7 PDF资料下载
参数资料
| 型号： | 8N3QV01EG-0011CDI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 19/23页 |
| 文件大小： | 0K |
| 描述： | IC VCXO LVPECL QD FREQUENCY 5X7 |
| 特色产品： | Fourth-generation FemtoClock for VCXO |
| 标准包装： | 1 |
| 系列： | FemtoClock® NG |
| 类型： | VCXO |
| 频率： | 可调节/可选择 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 电流 - 电源： | 150mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-CLCC |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-CLCC |
| 安装类型： | 表面贴装 |
| 其它名称： | 800-2572-6 |
IDT8N3QV01 Rev G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
IDT8N3QV01GCD REVISION A MARCH 6, 2012
5
2012 Integrated Device Technology, Inc.
Principles of Operation
The block diagram consists of the internal 3RD overtone crystal and
oscillator which provide the reference clock fXTAL of either 114.285
MHz or 100 MHz. The PLL includes the FemtoClock NG VCO along
with the Pre-divider (P), the feedback divider (M) and the post divider
(N). The P, M, and N dividers determine the output frequency based
on the fXTAL reference and must be configured correctly for proper
operation. The feedback divider is fractional supporting a huge
number of output frequencies. The configuration of the feedback
divider to integer-only values results in an improved output phase
noise characteristics at the expense of the range of output
frequencies. In addition, internal registers are used to hold up to four
different factory pre-set P, M, and N configuration settings. These
default pre-sets are stored in the I2C registers at power-up. Each
configuration is selected via the the FSEL[1:0] pins and can be read
back using the SCLK and SDATA pins.
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I2C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
If the user does choose to write a different P, M, and N configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I2C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The P, M, and N frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
The four configuration registers for the P, M (MINT & MFRAC) and N
dividers which are named Pn, MINTn, MFRACn and Nn with n=0 to
3. “n” denominates one of the four possible configurations.
As identified previously, the configurations of P, M (MINT & MFRAC)
and N divider settings are stored the I2C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information Section in this document. For
available order codes, see the FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information document.
For more information and guidelines on programming of the device
for custom frequency configurations, the register description, the pull
range programming and the serial interface description, see the
FemtoClock NG Ceramic 5x7 Module Programming Guide.
Table 4 Frequency Selection
Input
Selects
Register
FSEL1
FSEL0
0 (def.)
Frequency 0
P0, MINT0, MFRAC0, N0
0
1
Frequency 1
P1, MINT1, MFRAC1, N1
1
0
Frequency 2
P2, MINT2, MFRAC2, N2
1
Frequency 3
P3, MINT3, MFRAC3, N3
f
OUT
f
XTAL
1
PN
------------
MINT
MFRAC
0.5
+
2
18
-----------------------------------
+
=
(1)
相关PDF资料 |
PDF描述 |
|---|---|
| MS27484E14A5SB | CONN PLUG 5POS STRAIGHT W/SCKT |
| MS27467T15B97PB | CONN PLUG 12POS STRAIGHT W/PINS |
| VI-B4D-IU-S | CONVERTER MOD DC/DC 85V 200W |
| MS27473T18F28SD | CONN PLUG 28POS STRAIGHT W/SCKT |
| VI-B44-IU-S | CONVERTER MOD DC/DC 48V 200W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 8N3QV01EG-0012CDI | 制造商:Integrated Device Technology Inc 功能描述:10-LEAD CERAMIC 5X7 - Bulk |
| 8N3QV01EG-0012CDI8 | 功能描述:可编程振荡器 RoHS:否 制造商:IDT 封装 / 箱体:5 mm x 7 mm x 1.5 mm 频率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 频率稳定性:+/- 50 PPM 电源电压:3.63 V 负载电容:10 pF 端接类型:SMD/SMT 输出格式:LVPECL 最小工作温度:- 40 C 最大工作温度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封装: |
| 8N3QV01EG-0013CDI | 制造商:Integrated Device Technology Inc 功能描述:10-LEAD CERAMIC 5X7 - Bulk |
| 8N3QV01EG-0013CDI8 | 功能描述:VCXO IC 622.08MHz, 672.1627MHz, 696.4217MHz, 715.5389MHz 10-CLCC 制造商:idt, integrated device technology inc 系列:FemtoClock? NG 包装:带卷（TR） 零件状态:有效 类型:VCXO 计数:- 频率:622.08MHz，672.1627MHz，696.4217MHz，715.5389MHz 电压 - 电源:3.135 V ~ 3.465 V 电流 - 电源:150mA 工作温度:-40°C ~ 85°C 封装/外壳:10-CLCC 供应商器件封装:10-CLCC（7x5） 安装类型:表面贴装 标准包装:1,000 |
| 8N3QV01EG-0014CDI | 制造商:Integrated Device Technology Inc 功能描述:Controlled Oscillator 15.476MHz to 866.67MHz/975MHz to 1.3GHz VCXO LVPECL 10-Pin CLCC Tray 制造商:Integrated Device Technology Inc 功能描述:8N3QV01EG-0014CDI - Bulk 制造商:IDT 功能描述:IDT 8N3QV01EG-0014CDI Logic Misc |
发布紧急采购，3分钟左右您将得到回复。