参数资料
型号: 8N3QV01EG-0011CDI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 8/23页
文件大小: 0K
描述: IC VCXO LVPECL QD FREQUENCY 5X7
特色产品: Fourth-generation FemtoClock for VCXO
标准包装: 1
系列: FemtoClock® NG
类型: VCXO
频率: 可调节/可选择
电源电压: 2.375 V ~ 3.465 V
电流 - 电源: 150mA
工作温度: -40°C ~ 85°C
封装/外壳: 10-CLCC
包装: 标准包装
供应商设备封装: 10-CLCC
安装类型: 表面贴装
其它名称: 800-2572-6
IDT8N3QV01 Rev G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
IDT8N3QV01GCD REVISION A MARCH 6, 2012
16
2012 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8N3QV01.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8N3QV01 is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.75mW
Power (outputs)MAX = 34.2mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 519.75mW + 34.2mW = 533.95mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection
JA by Velocity
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
49.4°C/W
44.2C/W
41°C/W
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