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参数资料
| 型号： | 9248BF-81LFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, GREEN, SSOP-48 |
| 文件页数： | 9/20页 |
| 文件大小： | 568K |
| 代理商： | 9248BF-81LFT |
17
ICS9248- 81I
Advance Information
0851—08/06/03
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and ground
traces as wide as the via pad for
lower inductance.
Notes:
1) All clock outputs should have a
series terminating resistor, and a
20pF capacitor to ground between
the resistor and clock pin. Not
shown in all places to improve
readibility of diagram.
2) Optional crystal load capacitors
are recommended.They should be
included in the layout but not
inserted unless needed.
Connections toVDD:
C1
C4
1
Clock Load
C3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
Ferrite
Bead
VDD
C2
22F/20V
Tantalum
Ferrite
Bead
VDD
C2
22F/20V
Tantalum
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Ground
2.5V Power Route
3.3V Power Route
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