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| 型号： | 935261296529 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封装： | PEDESTAL, PLASTIC, MO-047, SOT-188-3, LCC-68 |
| 文件页数： | 17/52页 |
| 文件大小： | 303K |
| 代理商： | 935261296529 |
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Philips Semiconductors
Product specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
2001 Feb 13
24
Table 12.
IMR - Interrupt Mask Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O Port change
of state
Receiver Watch-dog
Time-out
Address
recognition event
Xon/off event
Set to 0
Change of
Break State
RxRDY
interrupt
TxRDY
interrupt
The programming of this register selects which bits in the ISR cause
an interrupt output. If a bit in the ISR is a ’1’ and the corresponding
bit in the IMR is a ’1’, the interrupt source is presented to the internal
interrupt arbitration circuits, eventually resulting in the IRQN output
being asserted (low). If the corresponding bit in the IMR is a zero,
the state of the bit in the ISR has no affect on the IRQN output.
IMR[7] - Controls if a change of state in the inputs equipped with
input change detectors will cause an interrupt.
IMR[6] - Controls the generation of an interrupt by the watch-dog
timer event. If set, a count of 64 idle bit times in the receiver will
begin interrupt arbitration.
IMR[5] - Enables the generation of an interrupt in response to
changes in the Address Recognition circuitry of the Special Mode
(multi-drop or wake-up mode).
IMR[4] - Enables the generation of an interrupt in response to
recognition of an in-band flow control character.
IMR[3] - Reserved
IMR[2] - Enables the generation of an interrupt when a Break
condition has been detected by the channel receiver.
IMR[1] - Enables the generation of an interrupt when servicing for
the RxFIFO is desired.
IMR[0] - Enables the generation of an interrupt when servicing for
the TxFIFO is desired.
Table 13.
RxFIFO Receiver FIFO
Bit[10]
Bit[9]
Bit[8]
Bits [7:0]
Break
Received
Status
Framing
Error
Status
Parity
Error
Status
8 data bits
MSBs =0 for 7,6,5 bit
data
The FIFO for the receiver is 11 bits wide and 16 “words” deep. The
status of each byte received is stored with that byte and is moved
along with the byte as the characters are read from the FIFO. The
upper three bits are presented in the STATUS register and they
change in the status register each time a data byte is read from the
FIFO. Therefor the status register should be read BEFORE the byte
is read from the RxFIFO if one wishes to ascertain the quality of the
byte
The forgoing applies to the “character error” mode of status
reporting. See MR1[5] and “RxFIFO Status” descriptions for “block
error” status reporting. Briefly “Block Error” gives the accumulated
error of all bytes received in the RxFIFO since the last “Reset Error”
command was issued. (CR = x’04)
Table 14.
TxFIFO - Transmitter FIFO
Bits 7:0
8 data bits. MSBs set to 0 for 7, 6, 5 bit data
The FIFO for the transmitter is 8 bits wide by 16 bytes deep. For
character lengths less than 8 bits the upper bits will be ignored by
the transmitter state machine and thus are effectively discarded.
Table 15.
BCRBRK - Bidding Control Register -
Break Change
Bits 7:3
Bits 2:0
Reserved
MSB of break change interrupt bid
This register provides the 3 MSBs of the Interrupt Arbitration number
for a break change interrupt.
Table 16.
BCRCOS - Bidding Control Register -
Change of State
Bits 7:3
Bits 2:0
Reserved
MSB of a COS interrupt bid
Read as x’0
This register provides the 3 MSBs of the Interrupt Arbitration number
for a Change of State, COS, interrupt.
Table 17.
BCRx - Bidding Control Register -
Xon/Xoff
Bits 7:3
Bits 2:0
Reserved
MSB of an Xon/Xoff interrupt bid
This register provides the 3 MSBs of the Interrupt Arbitration number
for an Xon/Xoff interrupt.
Table 18.
BCRA - Bidding Control Register -
Address
Bits 7:3
Bits 2:0
Reserved
MSB of an address recognition event
interrupt bid
This register provides the 3 MSBs of the Interrupt Arbitration number
for an address recognition event interrupt.
Table 19.
XonCR - Xon Character Register
Bits 7:0
8 Bits of the Xon Character Recognition
An 8 bit character register that contains the compare value for an
Xon character.
Table 20.
XoffCR - Xoff Character Register
Bits 7:0
8 Bits of the Xoff Character Recognition
An 8 bit character register that contains the compare value for an
Xoff character.
Table 21.
ARCR - Address Recognition Character
Register
Bits 7:0
8 Bits of the Multi-Drop Address Character Recognition
An 8 bit character register that contains the compare value for the
wake-up address character.
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