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| 型号： | 935261296529 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封装： | PEDESTAL, PLASTIC, MO-047, SOT-188-3, LCC-68 |
| 文件页数： | 9/52页 |
| 文件大小： | 303K |
| 代理商： | 935261296529 |
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Philips Semiconductors
Product specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
2001 Feb 13
17
Table 3.
MR0- Mode Register 0
See “XISR” for more descriptions of MR0 Xon/Xoff functions
Bit 7
Bit 6
Bit 5:4
Bit 3:2
Bit 1:0
Xon/Xoff * transparency
Address Recognition *
transparency
TxINT
In-band flow control mode
Address Recognition
control
1 - flow control characters
received are pushed onto
the RxFIFO
0 - flow control characters
received are not pushed
onto the RxFIFO
1 - Address characters
received are pushed to
RxFIFO
0 - Address characters
received are not pushed
onto the RxFIFO
TxFIFO interrupt
level control
00 - empty
01 - 3/4 empty
10 - 1/2 empty
11 - not full
00 - host mode, only the host CPU
may initiate flow control actions
through the CR
01 - Auto Transmitter flow control
10 - Auto Receiver flow control
11 - Auto Rx and Tx flow control
00 - none
01 - Auto wake
10 - Auto doze
11 - Auto wake and auto
doze
*
If these bits are not 0 the characters will be stripped regardless of bits (3:2) or (1:0)
MR0[7 & 6] - Control the handling of recognized Xon/Xoff or
Address characters. If set, the character codes are placed on the
RxFIFO along with their status bits just as ordinary characters are. If
the character is not pushed onto the RxFIFO, its received status will
be lost unless the receiver is operating in the block error mode (see
MR1[5] and the general discussion on receiver error handling).
Interrupt processing is not effected by the setting of these bits. See
Character recognition section.
MR0[5:4] - Controls the fill level at which a transmitter begins to
present its interrupt number to the interrupt arbitration logic. Use of a
low fill level minimizes the number of interrupts generated and
maximizes the number of transmit characters per interrupt cycle. It
also increases the probability that the transmitter will go idle for lack
of characters in the TxFIFO.
MR0[3:2] - Controls the Xon/Xoff processing logic. Auto Transmitter
flow control allows the gating of Transmitter activity by Xon/Xoff
characters received by the Channel’s receiver. Auto Receiver flow
control causes the Transmitter to emit an Xoff character when the
RxFIFO has loaded to a depth of 12 characters. Draining the
RxFIFO to a level of 8 or less causes the Transmitter to emit an Xon
character. All transmissions require no host involvement. A setting
other than b’00 in this field precludes the use of the command
register to transmit Xon/Xoff characters.
Note: Interrupt generation in Xon/Xoff processing is controlled by the
IMR (Interrupt Mask Register) of the individual channels. The
interrupt may be cleared by a read of the XISR, the Xon/Xoff
Interrupt Status Register. Receipt of a flow control character will
always generate an interrupt if the IMR is so programmed. The
MR0[3:2] bits have effect on the automatic aspects of flow control
only, not the interrupt generation.
MR0[1:0] - This field controls the operation of the Address
recognition logic. If the device is not operating in the special or
“wake-up” mode, this hardware may be used as a general purpose
character detector by choosing any combination except b’00.
Interrupt generation is controlled by the channel IMR. The XISR
interrupt and the XISR status bits may be cleared by a read of the
XISR. See further description in the section on the Wake-up mode.
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