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参数资料
| 型号： | 935261652118 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封装： | 7.50 MM, PLASTIC, SO-28 |
| 文件页数： | 2/31页 |
| 文件大小： | 176K |
| 代理商： | 935261652118 |
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1999 Oct 12
10
Philips Semiconductors
Product specication
IC card interface
TDA8002C
Table 1
Clock circuitry denition
Notes
1. X = don’t care.
2. In low-power mode.
3. fint = 32 kHz in low-power mode.
MODE
CLKSEL
CLKDIV1
CLKDIV2
FREQUENCY OF
CLK
FREQUENCY OF
CLKOUT
HIGH
LOW
HIGH
LOW
1
2fint
1
2fint
HIGH
LOW
1
4fxtal
fxtal
HIGH
LOW
HIGH
1
2fxtal
fxtal
HIGH
LOW
HIGH
STOP low
fxtal
HIGH
X(1)
STROBE
fxtal
LOW(2)
X(1)
STOP low
1
2fint(3)
I/O circuitry
The three I/O transceivers are identical. The state is HIGH
for all I/O pins (i.e. I/O, I/OUC, AUX1, AUX1UC, AUX2 and
AUX2UC). Pin I/O is referenced to VCC and pin I/OUC to
VDD, thus ensuring proper operation in the event that
VCC ≠ VDD.
The first side on which a falling edge is detected becomes
a master (input). An anti-latch circuitry first disables the
detection of the falling edge on the other side, which
becomes slave (output), see Fig.8.
After a delay time td (between 50 and 400 ns), the logic 0
present on the master side is transferred on the slave side.
When the input is back to HIGH level, a current booster is
turned on during the delay td on the output side and then
both sides are back to their idle state, ready to detect the
next logic 0 on any side.
In the event of a conflict, both lines may remain LOW until
the software enables the lines to be HIGH. The anti-latch
circuitry ensures that the lines do not remain LOW if both
sides return HIGH, regardless of the prior conditions.
The maximum frequency on the lines is approximately
200 kHz.
When CS is HIGH, I/OUC, AUX1UC and AUX2UC are
internally pulled-up to VDD with 20 k resistors. When
CS is LOW, I/OUC, AUX1UC and AUX2UC are
permanently HIGH (with integrated 100 k
pull-up
resistors connected to VDD).
Fig.8 Master and slave signals.
handbook, full pagewidth
td
MGD703
td
I/O
I/OUC
conflict
idle
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