- 您现在的位置：买卖IC网 > PDF目录122717 > 935262403118 (NXP SEMICONDUCTORS) 0 TIMER(S), REAL TIME CLOCK, PDSO8 PDF资料下载
参数资料
| 型号： | 935262403118 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封装： | 3 MM, PLASTIC, TSSOP-8 |
| 文件页数： | 6/32页 |
| 文件大小： | 711K |
| 代理商： | 935262403118 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
Philips Semiconductors
PCF8563
Real-time clock/calendar
Product specication
16 April 1999
14 of 30
9397 750 04855
Philips Electronics N.V. 1999. All rights reserved.
8.9.3
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal; see Figure 8.
8.9.4
Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related
clock pulse.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte. Also a master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 8.
Bit transfer on the I2C-bus.
dth
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 9.
Acknowledge on the I2C-bus.
width
MBC602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
相关PDF资料 |
PDF描述 |
|---|---|
| 935261475512 | 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84 |
| 9LPRS365BKLF | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 91W-G28AC-6-CG9 | SINGLE COLOR DISPLAY CLUSTER, GREEN, 7.1 mm |
| 91W-G5AC-6-CW0 | SINGLE COLOR DISPLAY CLUSTER, GREEN, 7.1 mm |
| 94W-EAY2-S0 | SINGLE COLOR LED, AMBER, 8.5 mm |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
发布紧急采购，3分钟左右您将得到回复。