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参数资料
| 型号： | 935268664112 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56 |
| 文件页数： | 16/16页 |
| 文件大小： | 99K |
| 代理商： | 935268664112 |
Philips Semiconductors
Product specification
PCK2010RA
CK98R (100/133MHz) RCC spread spectrum
system clock generator
2001 Apr 02
9
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
THKP
IOAPIC CLK period
60.0
61.2
60.0
61.2
ns
2, 9
THKH
IOAPIC CLK HIGH time
25.5
n/a
25.5
n/a
ns
5, 10
THKL
IOAPIC CLK LOW time
25.3
n/a
25.3
n/a
ns
6, 10
THRISE
IOAPIC CLK rise time
0.4
1.6
0.4
1.6
ns
8
THFALL
IOAPIC CLK fall time
0.4
1.6
0.4
1.6
ns
8
TJITTER
IOAPIC CLK cycle-cycle jitter
500
ps
DUTY CYCLE
IOAPIC CLK Duty Cycle
45
55
45
55
%
1
THSKW
IOAPIC CLK pin-pin skew
250
ps
2
3V66 CLOCK OUTPUT, 3V66 (0–3) (LUMP CAPACITANCE TEST LOAD = 30 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
THKP
3V66 CLK period
15.0
15.3
15.0
15.3
ns
2, 9, 4
THKH
3V66 CLK HIGH time
4.95
n/a
4.95
n/a
ns
5, 10
THKL
3V66 CLK LOW time
4.55
n/a
4.55
n/a
ns
6, 10
THRISE
3V66 CLK rise time
0.5
2.0
0.5
2.0
ns
8
THFALL
3V66 CLK fall time
0.5
2.0
0.5
2.0
ns
8
TJITTER
3V66 CLK cycle-cycle jitter
500
ps
DUTY CYCLE
3V66 CLK Duty Cycle
45
55
45
55
%
1
THSKW
3V66 CLK pin-pin skew
250
ps
2
48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
UNIT
NOTES
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNIT
NOTES
MIN
MAX
MIN
MAX
THKP
48 MHz clock period
20.829
20.83
20.829
20.83
ns
2
THKH
48 MHz clock HIGH time
7.57
n/a
7.57
n/a
ns
THKL
48 MHz clock LOW time
7.17
n/a
7.17
n/a
ns
THRISE (tR)
Output rise edge rate
1
4
1
4
ns
THFALL (tF)
Output fall edge rate
1
4
1
4
ns
DUTY CYCLE (tD)
Duty Cycle
45
55
45
55
%
TJITTER
CLK cycle-cycle jitter
500
ps
THSTB (fST)
Frequency stabilization from Power-up (cold start)
3
ms
NOTES:
1. See Figure 5 for measure points.
2. Average period over 1
s.
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