- 您现在的位置：买卖IC网 > PDF目录24830 > 935269256557 (NXP SEMICONDUCTORS) 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80 PDF资料下载
参数资料
| 型号： | 935269256557 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件页数： | 15/36页 |
| 文件大小： | 145K |
| 代理商： | 935269256557 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
2000 Nov 17
22
Philips Semiconductors
Preliminary specication
1394 SBP-2 link layer controller
SAA7356HL
Notes
1. ATA Multi-word Direct Memory Access (MDMA) protocol with all timing based on an internal DMA interface 50 MHz
system clock.
2. MICRO_ALE must pulse to capture a new register address for the Intel 8031 and the NEC V851 modes.
3. t10 must also be satisfied.
4. If MICRO_READ is held LOW, the time from MICRO_CS LOW to stable data is t5 and the data release time from
MICRO_CS HIGH is t11.
5. This is larger than the typical read strobe timing. To meet these requirements, either the microcontroller clock will be
stopped by the buffer manager device, or the microcontroller must insert its own wait states.
6. t5 must also be satisfied.
7. If MICRO_WRITE is held LOW, data set-up to MICRO_CS HIGH is t15 and data hold from MICRO_CS is t16.
8. t3 minimum = 2 × 3tCP + 5 for successive FIFO reads or a FIFO read or write followed by a read of the FIFO flag
registers.
9. This time relates to accesses to addresses other than RAM.Next and RAM.Current.
10. This time relates to accesses to the addresses RAM.Next and RAM.Current.
PHY-LINK INTERFACE TIMING; see Figs 14 and 15
t1
PHY-Link set-up time
6
ns
t2
PHY-Link hold time
0
ns
t3
PHY-Link output delay
2
10
ns
REGISTER INTERFACE TIMING; see Figs 16, 17, 18, 19, 20, 21 and 22
t1
address set-up to MICRO_ALE LOW
10
ns
t2
address hold from MICRO_ALE LOW
10
ns
t3
MICRO_ALE pulse width
note 2
20
ns
t4
MICRO_ALE LOW to MICRO_CS LOW
10
ns
t5
MICRO_CS LOW to data valid
note 3
280
ns
t6
MICRO_CS HIGH to MICRO_ALE HIGH
0
ns
t7
MICRO_CS set-up to MICRO_READ LOW
note 4
0
ns
t8
MICRO_READ pulse width
note 5
280
ns
t9
MICRO_READ HIGH to MICRO_CS HIGH
note 4
0
ns
t10
MICRO_READ LOW to data valid
note 6
280
ns
t11
MICRO_READ HIGH to data bus disable
2
30
ns
t12
MICRO_CS set-up to MICRO_WRITE LOW
note 7
0
ns
t13
MICRO_WRITE pulse width
30
ns
t14
MICRO_WRITE HIGH to MICRO_CS HIGH
note 7
0
ns
t15
data set-up to MICRO_WRITE HIGH
15
ns
t16
data hold from MICRO_WRITE HIGH
4
ns
t17
MICRO_WRITE HIGH to MICRO_ALE HIGH
note 8
tCP +5
ns
t18
MICRO_WRITE HIGH to MICRO_WRITE HIGH
note 9
280
ns
note 10
460
ns
t19
MICRO_READ LOW to MICRO_WAIT LOW
4ns
t20
data valid to MICRO_WAIT HIGH
20
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
相关PDF资料 |
PDF描述 |
|---|---|
| 935264570557 | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80 |
| 0803-7700-02 | Integrated VDSL Filter/Hybrid Solution |
| 935269451118 | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 935269451112 | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 0803-7700-03 | VDSL / PSTN CO Splitter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
| 935269544557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3 |
| 935269987557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557 |
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
| 935270792551 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
发布紧急采购，3分钟左右您将得到回复。