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参数资料
| 型号： | 935269256557 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件页数： | 2/36页 |
| 文件大小： | 145K |
| 代理商： | 935269256557 |
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2000 Nov 17
10
Philips Semiconductors
Preliminary specication
1394 SBP-2 link layer controller
SAA7356HL
In slave mode a buffer data transfer begins when the
DMA interface asserts the DMA_REQ pin. The buffer
manager responds with the DMA_ACK signal. The burst
configuration defines the number of bytes/words to keep
DMA_REQ asserted. The settings include:
DMA_REQ is asserted until the last byte/word is
transferred or until there is no space/data available in
the FIFO
DMA_REQ is asserted and negated for each byte/word
transferred
DMA_REQ is not asserted unless there is space/data
available in the FIFO
the DMA interface waits until there are at least two
bytes/words of data/space in the FIFO before asserting
DMA_REQ (in this case, DMA_REQ remains asserted
for the two bus transfers and then de-asserts); and
the DMA interface waits until there are at least four
bytes/words of data/space in the FIFO before asserting
DMA_REQ (in this case, DMA_REQ remains asserted
for the four bus transfers and then de-asserts).
This process repeats until all of the data is transferred. In
slave mode, there are three modes of operation for moving
data between the SAA7356HL and the DMA interface:
Mode 0: DMA_WRITE strobes the data from the buffer
memory data bus into the FIFO; DMA_READ gates the
data from the FIFO onto the buffer memory data bus
Mode 1: DMA_WRITE strobes the data from the buffer
memory into the FIFO. DMA_ACK gates data from the
FIFO onto the buffer memory data bus
Mode 2: DMA_ACK strobes the data from the buffer
memory bus into the FIFO and also gates the data from
the FIFO onto the buffer memory data bus.
In slave mode the DMA interface drives the DMA_REQ pin
and waits for the buffer manager to acknowledge the
request via DMA_ACK as described above. In master
mode, the buffer manager drives the DMA_REQ pin and
the DMA interface acknowledges the availability of
data/space with the DMA_ACK pin.
The read or write strobes are driven by the buffer manager
in slave mode, and by the DMA interface in master mode.
All mode selections listed above are also valid in master
mode, however it should be noted that the burst
configuration is not applicable in master mode.
Burst size in master mode is determined by the buffer
manager request signal, and DMA interface flow control by
the time duration between successive acknowledge
assertions or read/write assertions.
In master mode the SAA7356HL appears to be an
Advanced Technology Attachment (ATA) host and can be
connected to an ATA or Advanced Technology
Attachment Packet Interface (ATAPI) peripheral. The
SAA7356HL output signal (DMA_REQ) behaves like the
acknowledge on the Integrated Drive Electronics (IDE)
bus; the input signal (DMA_ACK) behaves like the request
line on the IDE bus.
The configuration information is provided via a
communication page which is shared between the
microcontroller and the SAA7356HL. The connections for
the various modes are shown in Figs 4 and 5.
7.4
Microcontroller interface
Because of the high-level protocol support, only ten
addresses are required. The user should note that all of
the internal SAA7356HL registers are still accessible and
so the chip-select line should be used to ensure that the
SAA7356HL is not accessed accidentally. The behaviour
on accessing these other addresses is not specified.
When used in V851 and H8 modes, the MICRO_WAIT line
is asserted within 4 ns of the MICRO_READ falling edge.
For all modes of operation, the data bus is the
MICRO_DATA bus. The microcontroller interface can be
configured for four modes of operation, namely:
Mode 0: 8-bit addressed Intel 8031 peripheral
(multiplexed address/data bus)
Mode 1: 8-bit addressed Hitachi H8 peripheral
(non-multiplexed address and data buses)
Mode 2: 16-bit addressed Intel 8031 peripheral (lower
address from multiplexed address/data bus)
Mode 3: 16-bit addressed NEC V851 peripheral (acting
as an 8-bit peripheral).
7.4.1
INTEL 8031 INTERFACE SUPPORT
The microcontroller interface logic supports the industry
standard 8031 style interface.
On reading, the MICRO_DATA output is enabled as soon
as the MICRO_READ is asserted. Before this happens,
the address will have already been decoded and the
internal Data Out signal asserted. On writing, the data is
loaded from the rising edge of MICRO_WRITE.
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