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参数资料
| 型号： | 93716YGLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93716 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | LEAD FREE, MO-150, SSOP-28 |
| 文件页数： | 1/13页 |
| 文件大小： | 115K |
| 代理商： | 93716YGLF-T |
Integrated
Circuit
Systems, Inc.
ICS93716
0420H—09/10/08
Block Diagram
Low Cost DDR Phase Lock Loop Clock Driver
Pin Configuration
28-Pin SSOP and TSSOP
Recommended Application:
DDR Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
I
2C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Bypass mode on B revision only
Switching Characteristics:
PEAK - PEAK jitter (66MHz): <75ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 550ps - 950ps
Functionality
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U
P
N
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S
L
P
D
V
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N
I
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K
L
CC
N
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L
CT
K
L
CC
K
L
CT
T
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B
FC
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B
D
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a
p
y
B
FB_INT
FB_INC
CLK_INC
CLK_INT
SCLK
SDATA
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
PLL
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
CLKT2
CLKC2
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
FBINC
FBINT
FB_OUTT
FB_OUTC
CLKT3
CLKC3
GND
ICS93716
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2
3
4
5
6
7
8
9
10
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12
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14
28
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相关PDF资料 |
PDF描述 |
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| 93716YFLF-T | 93716 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 93716BGLFT | 93716 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 93718CFLF | 93718 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48 |
| 93718CFLFT | 93718 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48 |
| 93722CFLF | 93722 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
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| 937-17MM | 功能描述:支架与垫片 Plastic Spcr 17mm Nylon White RoHS:否 制造商:Schurter 类型:Transipillar Spacers 长度:16 m 螺纹大小:M4 外径:10 mm 材料:Nylon with Steel 电镀:Zinc |
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