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参数资料
| 型号： | 93AA56-I/SM |
| 元件分类： | PROM |
| 英文描述： | 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.207 INCH, PLASTIC, SOIC-8 |
| 文件页数： | 8/13页 |
| 文件大小： | 102K |
| 代理商： | 93AA56-I/SM |
93AA46/56/66
DS20067H-page 4
1998 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
When the ORG pin is connected to VCC, the (x16) orga-
nization is selected. When it is connected to ground,
the (x8) organization is selected.
Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is nor-
mally held in a high-Z state except when reading data
from the device, or when checking the READY/BUSY
status during a programming operation. The ready/
busy status can be veried during an Erase/Write oper-
ation by polling the DO pin; DO low indicates that pro-
gramming is still in progress, while DO high indicates
the device is ready. The DO will enter the high-Z state
on the falling edge of the CS.
2.1
START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the rst time.
Before a START condition is detected, CS, CLK, and
DI may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this conguration it is possible
for a “bus conict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic
HIGH level. Under such a condition the voltage level
seen at Data Out is undened and will depend upon the
relative impedances of Data Out and the signal source
driving A0. The higher the current sourcing capability
of A0, the higher the voltage at the Data Out pin.
2.3
Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V at nominal conditions.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
2.4
READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specied time delay (TPD). Sequential read is
possible when CS is held high. The memory data will
automatically cycle to the next register and output
sequentially.
2.5
Erase/Write Enable and Disable
(EWEN,EWDS)
The 93AA46/56/66 power up in the Erase/Write Dis-
able (EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruc-
tion. Once the EWEN instruction is executed, program-
ming remains enabled until an EWDS instruction is
executed or VCC is removed from the device. To pro-
tect against accidental data disturb, the EWDS instruc-
tion can be used to disable all Erase/Write functions
and should follow all programming operations. Execu-
tion of a READ instruction is independent of both the
EWEN and EWDS instructions.
2.6
ERASE
The ERASE instruction forces all data bits of the spec-
ied address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specied address has been erased
and the device is ready for another instruction.
The ERASE cycle takes 4 ms per word typical.
2.7
WRITE
The WRITE instruction is followed by 16 bits (or by 8
bits) of data which are written into the specied
address. After the last data bit is put on the DI pin, CS
must be brought low before the next rising edge of the
CLK clock. This falling edge of CS initiates the self-
timed auto-erase and programming cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is com-
plete. DO at logical “0” indicates that programming is
still in progress. DO at logical “1” indicates that the reg-
ister at the specied address has been written with the
data specied and the device is ready for another
instruction.
The WRITE cycle takes 4 ms per word typical.
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| 93AA56XT-I/SM | 256 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 93AA56-P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 1.8V Microwire Serial EEPROM |
| 93AA56-SM | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 1.8V Microwire Serial EEPROM |
| 93AA56-SN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 1.8V Microwire Serial EEPROM |
| 93AA56T/P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K/2K/4K 1.8V Microwire Serial EEPROM |
| 93AA56T/SM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SERIAL EEPROM|256X8/128X16|CMOS|SOP|8PIN|PLASTIC |
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