参数资料
型号: 93AA56-I/SM
元件分类: PROM
英文描述: 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封装: 0.207 INCH, PLASTIC, SOIC-8
文件页数: 9/13页
文件大小: 102K
代理商: 93AA56-I/SM
1998 Microchip Technology Inc.
DS20067H-page 5
93AA46/56/66
2.8
Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the self clocking mode. The ERAL instruction is guar-
anteed at 5V
± 10%.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is com-
plete.
The ERAL cycle takes (8 ms typical).
2.9
Write All (WRAL)
The WRAL instruction will write the entire memory
array with the data specied in the command. The
WRAL cycle is completely self-timed and commences
at the falling edge of the CS. Clocking of the CLK pin
is not necessary after the device has entered the self
clocking mode. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status. The WRAL
instruction is guaranteed at 5V
± 10%.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The WRAL cycle takes 16 ms typical.
FIGURE 2-1:
SYNCHRONOUS DATA TIMING
FIGURE 2-2:
READ TIMING
CLK
STATUS VALID
VIH
VIL
CS
TCSS
TDIS
TDIH
TSV
TCSH
TCKH
TCKL
TPD
TCZ
TPD
VIH
VIL
DI
VIH
VIL
DO
(READ)
VOH
VOL
DO
(PROGRAM)
VOH
VOL
Tri-State is a registered trademark of National Semiconductor Incorporated.
CLK
CS
TCSL
A
A0
0
1
DI
DO
Dx
D0
0
Dx*
D0
Dx*
TRI-STATE
n
D0
TRI-
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