参数资料
型号: 93AA66T-I/SN
厂商: Microchip Technology
文件页数: 7/22页
文件大小: 0K
描述: IC EEPROM 4KBIT 2MHZ 8SOIC
标准包装: 3,300
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 4K(512 x 8 或 256 x 16)
速度: 1MHz,2MHz
接口: Microwire 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
93AA46/56/66
2.7
Write
The DO pin indicates the Ready/Busy status of the
The WRITE instruction is followed by 16 bits (or by 8
bits) of data which are written into the specified
address. After the last data bit is put on the DI pin,
device if CS is brought high after a minimum of 250 ns
low (T CSL ) and before the entire write cycle is complete.
The ERAL cycle takes (8 ms typical).
CS must be brought low before the next rising edge
of the CLK clock. This falling edge of CS initiates the
2.9
Write All ( WRAL )
self-timed auto-erase and programming cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T CSL ) and before the entire write cycle is complete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another
instruction.
The write cycle takes 4 ms per word typical.
The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences at the
falling edge of the CS. Clocking of the CLK pin is not
necessary after the device has entered the Self Clock-
ing mode. The WRAL command does include an auto-
matic ERAL cycle for the device. Therefore, the WRAL
instruction does not require an ERAL instruction but the
chip must be in the EWEN status. The WRAL instruction
is ensured at 5V ± 10%.
The DO pin indicates the Ready/Busy status of the
2.8
Erase All ( ERAL )
device if CS is brought high after a minimum of 250 ns
The ERAL instruction will erase the entire memory array
to the logical “1” state. The ERAL cycle is identical to
the erase cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
at the falling edge of the CS. Clocking of the CLK pin is
not necessary after the device has entered the Self
Clocking mode. The ERAL instruction is ensured at 5V
± 10%.
low (T CSL ).
The WRAL cycle takes 16 ms typical.
FIGURE 2-1:
V IH
CS
SYNCHRONOUS DATA TIMING
V IL
T CSS
T CKH
T CKL
T CSH
V IH
CLK
V IL
DI
V IH
V IL
T DIS
T DIH
V OH
DO
(Read) V OL
T SV
T PD
T PD
T CZ
T CZ
V OH
DO
(Program) V OL
? 2004 Microchip Technology Inc.
Status Valid
DS20067J-page 7
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