参数资料
型号: 93LC56BXT/SNA24
元件分类: PROM
英文描述: 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封装: 0.150 INCH, PLASTIC, SOIC-8
文件页数: 8/12页
文件大小: 222K
代理商: 93LC56BXT/SNA24
93LC56A/B
1998 Microchip Technology Inc.
DS21208C-page 5
3.4
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
3.5
Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2:
ERASE TIMING
FIGURE 3-3:
ERAL TIMING
CS
CLK
DI
DO
TCSL
CHECK STATUS
1
1AN
AN-1
AN-2
A0
TSV
TCZ
BUSY
READY
HIGH-Z
TWC
HIGH-Z
CS
CLK
DI
DO
TCSL
CHECK STATUS
10
0
1
0
X
X
TSV
TCZ
BUSY
READY
HIGH-Z
TEC
HIGH-Z
Guaranteed at Vcc = 4.5V to +6.0V.
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