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参数资料
| 型号： | 9403A |
| 厂商： | Fairchild Semiconductor Corporation |
| 英文描述： | First-In First-Out (FIFO) Buffer Memory(先进先出缓冲器) |
| 中文描述： | 先入先出（FIFO）的缓冲存储器（先进先出缓冲器） |
| 文件页数： | 3/16页 |
| 文件大小： | 174K |
| 代理商： | 9403A |
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9
Functional Description
As shown in the block diagram the 49403A consists of
three sections:
1. An Input Register with parallel and serial data inputs as
well as control inputs and outputs for input handshak-
ing and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output hand-
shaking and expansion.
Since these three sections operate asynchronously and
almost independently, they will be described separately
below.
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessary status and
control signals.
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
the F
3
flip-flop and resetting the other flip-flops. The Q out-
put of the last flip-flop (FC) is brought out as the
“
Input
Register Full
”
output (IRF). After initialization this output is
HIGH.
Parallel Entry—
A HIGH on the PL input loads the D
0
-D
3
inputs into the F
0
-F
3
flip-flops and sets the FC flip-flop. This
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
Serial Entry—
Data on the D
S
input is serially entered into
the F
3
, F
2
, F
1
, F
0
, FC shift register on each HIGH-to-LOW
transition of the CPSI clock input, provided IES and PL are
LOW.
After the fourth clock transition, the four data bits are
located in the four flip-flops, F
0
-F
3
. The FC flip-flop is set,
forcing the IRF output LOW and internally inhibiting CPSI
clock pulses from affecting the register, Figure 2 illustrates
the final positions in a 9403A resulting from a 64-bit serial
bit train. B
0
is the first bit, B
63
the last bit.
FIGURE 1. Conceptual Input Section
FIGURE 2. Final Positions in a 9403A Resulting from a 64-Bit Serial Train
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9403A WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 9403ADMQB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Multi-Mode FIFO |
| 9403ADMQB | 制造商:National Semiconductor Corporation 功能描述:FIFO Register Single 4-CH 24-Pin CDIP 制造商:National Semiconductor 功能描述:FIFO Register Single 4-CH 24-Pin CDIP |
| 9403ALMQB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Multi-Mode FIFO |
| 9403APC | 功能描述:寄存器 FIFO Buffer Memory RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
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