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参数资料
| 型号： | 94211AFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, MO-118, SSOP-48 |
| 文件页数： | 15/18页 |
| 文件大小： | 157K |
| 代理商： | 94211AFT |
6
ICS94211
0441E—11/17/04
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
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B-
X
#
2
S
F
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t
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6
t
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B-
1
)
d
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R
(
5
t
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B-
1
)
d
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v
r
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s
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R
(
4
t
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B-
1
)
d
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v
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R
(
3
t
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B0
41
0
M
A
R
D
S
2
t
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B-
1
)
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R
(
1
t
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B3
41
1
K
L
C
U
P
C
0
t
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B4
41
0
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
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I
T
P
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7
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6
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(
4
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11
4
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3
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11
3
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2
t
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11
2
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1
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11
1
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P
0
t
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B8
1
0
K
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I
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P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
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5
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4
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3
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2
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1
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0
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1
)
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s
e
R
(
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
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I
T
P
I
R
C
S
E
D
7
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B-
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v
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R
(
6
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B-
1
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R
(
5
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B-
1
)
d
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v
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R
(
4
t
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B7
41
C
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P
A
O
I
3
t
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B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B-
1
)
d
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v
r
e
s
e
R
(
1
t
i
B6
41
1
F
E
R
0
t
i
B2
1
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
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B-
0
)
e
t
o
N
(
d
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v
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6
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B-
0
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t
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N
(
d
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v
r
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s
e
R
5
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B-
0
)
e
t
o
N
(
d
e
v
r
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s
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R
4
t
i
B-
0
)
e
t
o
N
(
d
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v
r
e
s
e
R
3
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0
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t
o
N
(
d
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v
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R
2
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i
B-
1
)
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N
(
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R
1
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1
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(
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0
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B-
0
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t
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N
(
d
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R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: This is an unused register writing to this register
will not affect device performance or functinality.
T
I
B#
N
I
PD
W
PN
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T
P
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R
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D
7
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6
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#
0
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5
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21
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