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参数资料
| 型号： | 94227AFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件页数： | 1/18页 |
| 文件大小： | 151K |
| 代理商： | 94227AFLFT |
Integrated
Circuit
Systems, Inc.
ICS94227
0446B—12/20/02
Block Diagram
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA Apollo Pro 266 style chipset.
Output Features:
3 - CPUs @ 2.5V, up to 200MHz.
3 - IOAPIC @ 2.5V, PCI frequency
9 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @ 3.3V, 14.318MHz.
3 - AGP @ 3.3V
Features:
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable group skew.
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
Provide all system clocks needed when used with a
memory clock fanout buffer like the ICS93718.
Skew Specifications:
CPU – CPU: <175ps
PCI – PCI: <500ps
CPU(early)-PCI: Min = 1.0ns, Max = 2.5ns
CPU Cycle to cycle jitter: < 250ps
CPU(early)-AGP: Max = 500ps
Programmable Frequency Generator for Celeron & PII/III
*
Internal Pull-up Resistor of 120K to VDD
FS (4:0)
PD#
CPU_STOP#
SDATA
SCLK
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (1:0)
CPUCLK2/F
IOAPIC (2:0)
RESET#
RATIO (1:0)
AGPCLK (2:0)
PCICLK (8:0)
9
3
2
X1
X2
XTAL
OSC
CPU
DIVDER
IOAPIC
DIVDER
AGP
DIVDER
PCI
DIVDER
Stop
Stop/F
Stop
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
4
S
F3
S
F2
S
F1
S
F0
S
F
U
P
C
)
z
H
M
(
P
G
A
)
z
H
M
(
K
L
C
I
C
P
)
z
H
M
(
0
000
0
.
0
20
0
.
0
80
0
.
0
4
00
0
1
0
.
0
9
10
0
.
6
70
0
.
8
3
00
0
1
0
.
0
8
10
0
.
2
70
0
.
6
3
00
0
1
0
.
0
7
10
0
.
8
60
0
.
4
3
00
1
0
.
6
10
4
.
6
60
2
.
3
00
1
0
1
0
.
0
6
10
0
.
4
60
0
.
2
3
00
1
0
.
0
5
10
0
.
5
70
5
.
7
3
0
111
0
.
5
4
10
5
.
2
75
2
.
6
3
0
1
000
0
.
0
4
10
0
.
0
70
0
.
5
3
01
0
1
0
.
6
3
10
0
.
8
60
0
.
4
3
01
0
1
0
.
0
3
10
0
.
5
60
5
.
2
3
01
0
1
0
.
4
2
10
0
.
2
60
0
.
1
3
01
1
0
7
6
.
6
67
6
.
6
64
3
.
3
01
1
0
1
0
.
0
17
6
.
6
63
3
.
3
01
1
0
.
8
1
17
6
.
8
73
3
.
9
3
0
1
111
3
.
3
17
6
.
6
64
3
.
3
VDDREF
GND
X1
X2
AVDD48
*FS3/48MHz
*FS2/24_48MHz
GND
PCICLK0
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
PCICLK7
GND
PCICLK8
*FS1/RATIO_1
*FS0/RATIO_0
AGPCLK0
VDDAGP
REF0
REF1/FS4*
VDDL
IOAPIC0
IOAPIC1
GND
IOAPIC2
VDDLCPU
GND
CPUCLK0
CPUCLK1
VDDL
GND
CPUCLK2/F
CPU_STOP#*
RESET#
PD*
AVDD
GND
SDATA
SCLK
AGPCLK2
AGPCLK1
GND
ICS94227
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Power Groups
AVDD= Core PLL
AVDD48 = 24, 48MHz and fixed PLL
VDDREF = REF clocks, Xtal
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