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参数资料
| 型号： | 94228BFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 233.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 1/19页 |
| 文件大小： | 189K |
| 代理商： | 94228BFLF |
Integrated
Circuit
Systems, Inc.
ICS94228
0447E—05/07/04
Block Diagram
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KT266 style chipset
Output Features:
1 - Differential pair open drain CPU clocks @ 2.7V
1 - Differential pair push-pull CPU clocks @ 2.5V
11 - PCI including 1 free running and 1 early @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Features:
Programmable output frequency.
Programmable output rise/fall time.
Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.
Real time system reset output.
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread
percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
Skew Specifications:
CPU - CPU: <200ps
PCI - PCI: <500ps
CPU (early - PCI: min=1.0ns, max=2.6ns
CPU cycle to cycle jitter: <250ps
Programmable System Clock Chip for AMD - K7 processor
* Internal Pull-up Resistor of 120K to VDD
SEL24_48#
PLL2
PLL1
Spread
Spectrum
48MHz (1:0)
24_48MHz
PCICLK (8:0)
AGP (2:0)
PCICLK_F
REF_F
PCICLK9_E
SRESET#
3
9
2
X1
X2
XTAL
OSC
CPU
DIVDER
CPU
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
AGP_STOP#
REF_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
CPUCLKT0
CPUCLKC0
CPUCLK_CST0
CPUCLK_CSC0
3
S
F2
S
F1
S
F0
S
F
U
P
C
)
z
H
M
(
P
G
A
)
z
H
M
(
K
L
C
I
C
P
)
z
H
M
(
0000
3
.
3
28
7
.
7
78
8
.
8
3
000
1
0
.
0
2
23
3
.
3
77
6
.
6
3
00
1
0
.
0
1
20
0
.
0
70
0
.
5
3
00
11
0
.
0
27
6
.
6
63
3
.
3
01
0
.
0
9
10
0
.
6
70
0
.
8
3
01
0
.
0
8
10
0
.
2
70
0
.
6
3
01
1
0
.
0
7
10
0
.
8
60
0
.
4
3
0
111
0
.
0
5
10
0
.
5
70
5
.
7
3
1
000
0
.
0
4
10
0
.
0
70
0
.
5
3
10
0
1
0
.
0
2
10
0
.
0
60
0
.
0
3
10
0
.
0
1
10
0
.
6
60
0
.
3
10
1
7
6
.
6
67
6
.
6
63
3
.
3
11
00
0
.
0
27
6
.
6
63
3
.
3
11
0
1
7
6
.
6
17
6
.
6
63
3
.
3
111
0
.
0
17
6
.
6
63
3
.
3
1111
3
.
3
17
6
.
6
63
3
.
3
VDDREF
GND
X1
X2
AVDD48
*FS2/48MHz
*FS3/24_48MHz
GND
PCICLK_F
*SEL24_48#/PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
PCILCK8
PCICLK9_E
VDDPCI
SRESET#
REF0/
REF1/FS1*
REF_F
REF_STOP#*
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
SDATA
SCLK
GND
AGP2
AGP1
AGP0
VDDAGP
FS0*
ICS9422
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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