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参数资料
| 型号： | 950902DGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56 |
| 文件页数： | 12/22页 |
| 文件大小： | 210K |
| 代理商： | 950902DGLFT |
2
Integrated
Circuit
Systems, Inc.
ICS950902
0475F—10/13/03
Pin Description
General Description
The ICS950902 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with
PC133 or DDR memory.
The ICS950902 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin description continued on next page.
PIN
#
NAME
TYPE
1
*FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
2
GND
PWR
Ground pin.
3
X1
IN
Crystal input,nominally 14.318MHz.
4
X2
OUT
Crystal output, Nominally 14.318MHz
5
VDDAGP
PWR
Power supply for AGP clocks, nominal 3.3V
6
*MODE/AGPCLK0
I/O
Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / AGP clock output.
7
*SEL_408/K7/AGPCLK1
I/O
CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output.
8
*(PCI_STOP#)AGPCLK2
I/O
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input
is activated by the MODE selection pin / AGP clock output.
9
GNDAGP
PWR
Ground pin for the AGP outputs
10
**FS1/PCICLK_F
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
11
**SEL_SDR/DDR#/PCICLK1
I/O
Memory type select latch input pin 0= DDR, 1= PC133 SDRAM / 3.3V PCI clock output.
12
*MULTSEL/PCICLK2
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock output.
13
GNDPCI
PWR
Ground pin for the PCI outputs
14
PCICLK3
OUT
PCI clock output.
15
PCICLK4
OUT
PCI clock output.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
PCICLK5
OUT
PCI clock output.
18
*(CLK_STOP#)PCICLK6
I/O
Stops all CPU, DDR/SDRAM and FB_OUT clocks at logic 0 level, when input low. This input
is activated by the MODE selection pin / PCI clock output.
19
GND48
PWR
Ground pin for the 48MHz outputs
20
*FS3/48MHz
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
21
*FS2/24_48MHz
I/O
Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
22
AVDD48
PWR
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
23
VDD
PWR
Power supply, nominal 3.3V
24
GND
PWR
Ground pin.
25
IREF
OUT
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
26
*(PD#)RESET#
I/O
Asynchronous active low input pin used to power down the device into a low power state.
This input is activated by the MODE selection pin / Real time system reset signal for
frequency gear ratio change or watchdog timer timeout. This signal is active low.
27
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
28
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
DESCRIPTION
~ This output has 2X drive strength
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