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参数资料
| 型号： | 952601YGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件页数： | 3/25页 |
| 文件大小： | 227K |
| 代理商： | 952601YGLFT |
IDTTM
Progammable Timing Control HubTM for Next Gen P4TM Processor
701J—01/25/10
ICS952601
Programmable Timing Control HubTM for Next Gen P4TM Processor
11
I
2C Table: Read-Back Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RESERVED
-
X
Bit 6
RESERVED
-
X
Bit 5
RESERVED
-
X
Bit 4
RESERVED
-
X
Bit 3
PCI_STOP#
PCI STOP# Read
Back
RX
Bit 2
CPU_STOP#
CPU STOP Read
Back
RX
Bit 1
FSB
Freq Select 1 Read
Back
RX
Bit 0
FSA
Freq Select 0 Read
Back
RX
I
2C Table: Spreading and Device Behavior Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC/SRC#
SRC Free-Running
Control
RW
FREE-RUN
STOPPABLE
0
Bit 6
SRC
Output Control
RW
Disable
Enable
1
Bit 5
CPUT2/CPUC2
RW
FREE-RUN
STOPPABLE
1
Bit 4
CPUT1/CPUC1
RW
FREE-RUN
STOPPABLE
1
Bit 3
CPUT0/CPUC0
RW
FREE-RUN
STOPPABLE
1
Bit 2
CPUT2/CPUC2
Output Control
RW
Disable
Enable
1
Bit 1
CPUT1/CPUC1
Output Control
RW
Disable
Enable
1
Bit 0
CPUT0/CPUC0
Output Enable
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC_PD#
Drive Mode
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 6
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW
Driven
Hi-Z
0
Bit 5
CPUT2_PD# Drive
Mode
RW
Driven
Hi-Z
0
Bit 4
CPUT1_PD# Drive
Mode
RW
Driven
Hi-Z
0
Bit 3
CPUT0_PD# Drive
Mode
RW
Driven
Hi-Z
0
Bit 2
CPUT2_Stop Drive
Mode
RW
Driven
Hi-Z
0
Bit 1
CPUT1_Stop Drive
Mode
RW
Driven
Hi-Z
0
Bit 0
CPUT0_Stop Drive
Mode
RW
Driven
Hi-Z
0
43,44
40,41
46,47
43,44
40,41
46,47
CPU FREE-
RUNNING
CONTROL
43,44
40,41
46,47
Byte 1
37,38
46,47
43,44
40,41
Byte 2
37,38
Byte 0
-
RESERVED
-
RESERVED
-
RESERVED
0:driven when
stopped
1: Tri-stated
0:driven in PD#
1: Tri-stated
-
READBACK
READBACK of CPU(2:0)
Frequency
READBACK
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