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| 型号： | 9DB106BGILFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28 |
| 文件页数： | 10/14页 |
| 文件大小： | 152K |
| 代理商： | 9DB106BGILFT |
IDT
Six Output Differential Buffer for PCIe Gen 2
9DB106
REV K 04/20/11
9DB106
Six Output Differential Buffer for PCIe Gen 2
5
Electrical Characteristics - Clock Input Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage -
DIF_IN
VIHDIF
Differential inputs
(single-ended measurement)
600
800
1150
mV
1
Input Low Voltage -
DIF_IN
VILDIF
Differential inputs
(single-ended measurement)
VSS - 300
0
300
mV
1
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
300
1000
mV
1
Input Amplitude - DIF_IN
VSWING
Peak to Peak value
300
1450
mV
1
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
0.4
8
V/ns
1,2
Input Leakage Current
IIN
VIN = VDD , VIN = GND
-5
5
uA
1
Input Duty Cycle
dtin
Measurement from differential
wavefrom
45
55
%
1
Input Jitter - Cycle to
Cycle
JDIFIn
Differential Measurement
0
125
ps
1
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - PLL Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
Min
Typ
Max
Units
Notes
PLL Jitter Peaking
jpeak-hibw
(PLL_BW = 1)
0
1
2.5
dB
1,4
PLL Jitter Peaking
jpeak-lobw
(PLL_BW = 0)
0
1
2
dB
1,4
PLL Bandwidth
pllHIBW
(PLL_BW = 1)
2
2.5
3
MHz
1,5
PLL Bandwidth
pllLOBW
(PLL_BW = 0)
0.4
0.5
1
MHz
1,5
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
40
108
ps
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=1)
2.7
3.1
ps rms
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
2.2
3.1
ps rms
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
1.3
3
ps rms
1,2,3
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
Jitter, Phase
tjphasePLL
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9DB106BGLF | 功能描述:时钟缓冲器 6 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB106BGLFT | 功能描述:时钟缓冲器 6 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB106CFLF | 制造商:Integrated Device Technology Inc 功能描述:9DB106CFLF - Rail/Tube |
| 9DB106CFLFT | 制造商:Integrated Device Technology Inc 功能描述:9DB106CFLFT - Tape and Reel |
| 9DB106CGLF | 制造商:Integrated Device Technology Inc 功能描述:9DB106CGLF - Rail/Tube |
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