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| 型号： | 9DB306BL |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 4.40 X 9.70 MM, 0.925 MM HEIGHT, TSSOP-28 |
| 文件页数： | 17/17页 |
| 文件大小： | 268K |
| 代理商： | 9DB306BL |
ICS9DB306BL REVISION C AUGUST 13, 2009
9
2009 Integrated Device Technology, Inc.
ICS9DB306 Data Sheet
PCI EXPRESS JITTER ATTENUATOR
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are de-
signed to drive 50
Ω transmission lines. Matched impedance
techniques should be used to maximize operating frequency
and minimize signal distortion.
Figures 4A and 4B show two
different layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be recom-
mended that the board designers simulate to guarantee com-
patibility across all printed circuit and clock component pro-
cess variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kW resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9DB306BLI | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 28TSSOP - Rail/Tube |
| 9DB306BLILF | 功能描述:IC JITTER ATTENUATOR 28-TSSOP 制造商:idt, integrated device technology inc 系列:- 包装:管件 零件状态:过期 PLL:是 主要用途:PCI Express（PCIe） 输入:HCSL，LVDS，LVHSTL，LVPECL，SSTL 输出:LVPECL 电路数:1 比率 - 输入:输出:1：6 差分 - 输入:输出:是/是 频率 - 最大值:140MHz 电压 - 电源:2.97 V ~ 3.63 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-TSSOP（0.173"，4.40mm 宽） 供应商器件封装:28-TSSOP 标准包装:50 |
| 9DB306BLILFT | 功能描述:IC JITTER ATTENUATOR 28-TSSOP 制造商:idt, integrated device technology inc 系列:- 包装:带卷（TR） 零件状态:过期 PLL:是 主要用途:PCI Express（PCIe） 输入:HCSL，LVDS，LVHSTL，LVPECL，SSTL 输出:LVPECL 电路数:1 比率 - 输入:输出:1：6 差分 - 输入:输出:是/是 频率 - 最大值:140MHz 电压 - 电源:2.97 V ~ 3.63 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-TSSOP（0.173"，4.40mm 宽） 供应商器件封装:28-TSSOP 标准包装:1,000 |
| 9DB306BLIT | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 28TSSOP - Rail/Tube |
| 9DB306BLLF | 功能描述:时钟合成器/抖动清除器 2 LVPECL Output PCI- Express Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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