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参数资料
| 型号： | 9DB633AGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28 |
| 文件页数： | 8/14页 |
| 文件大小： | 182K |
| 代理商： | 9DB633AGLFT |
IDT
Six Output Differential Buffer for PCIe Gen3
1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
3
Datasheet
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPT ION
1PLL_BW
IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
2
SRC_IN
IN
0.7 V Differential SRC TRUE input
3
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
4v OE1#
IN
Activ e low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
5DIF_0
OUT
0.7V differential true clock output
6
DIF_0#
OUT
0.7V differential Complementary clock output
7
VDD
PWR
Power supply, nominal 3.3V
8
GND
IN
Ground pin.
9
DIF_1
OUT
0.7V differential true clock output
10
DIF_1#
OUT
0.7V differential Complementary clock output
11
DIF_2
OUT
0.7V differential true clock output
12
DIF_2#
OUT
0.7V differential Complementary clock output
13
VDD
PWR
Power supply, nominal 3.3V
14
SMBDAT
I/O
Data pin of SMBUS c ircuitry, 5V tolerant
15
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
16
VDD
PWR
Power supply, nominal 3.3V
17
DIF_3#
OUT
0.7V differential Complementary clock output
18
DIF_3
OUT
0.7V differential true clock output
19
DIF_4#
OUT
0.7V differential Complementary clock output
20
DIF_4
OUT
0.7V differential true clock output
21
GND
PWR
Ground pin.
22
VDD
PWR
Power supply, nominal 3.3V
23
DIF_5#
OUT
0.7V differential Complementary clock output
24
DIF_5
OUT
0.7V differential true clock output
25
v OE4#
IN
Activ e low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
26
IREF
OUT
T his pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precis ion resistor to ground. 475ohm is the s tandard value for
100ohm differential impedance. Other impedances require different v alues. See
data sheet.
27
GNDA
PWR
Ground pin for the PLL c ore.
28
VDDA
PWR
3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
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| 9DB633AFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9DB801BFLF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB801BFLFT | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB801BGLF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB801BGLFT | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB801CFLF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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