参数资料
型号: 9DB833AGILFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封装: ROHS COMPLIANT, TSSOP-48
文件页数: 17/18页
文件大小: 226K
代理商: 9DB833AGILFT
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
8
9DB833
REV C 052411
Electrical Characteristics–PCIe Phase Jitter Parameters
Clock Periods Differential Outputs Tracking Spread Spectrum
Clock Periods Differential Outputs not Tracking Spread Spectrum
TA = TCOM or TI ND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
tjphPCIeG1
PCIe Gen 1
30
86
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.0
3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MH z)
2.2
3.1
ps
(rms)
1,2
tjphPCIeG3
PC Ie Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.5
1
ps
(rms)
1,2,4
t
jphPC IeG1
PCIe Gen 1
1
5
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MH z)
0.2
0.3
ps
(rms)
1,2
t
jphPC IeG3
PC Ie Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.0
0.1
ps
(rms)
1,2,4
1 Applies to all outputs.
4 Subject to final radification by PCI SIG.
tjphPCIeG2
2
See http://www.pcisig.com for complete specs
tjphPCIeG2
Phase Jitter, PLL Mode
Additive Phase Jitter, Bypass
Mode
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
1 Clock
1us
0.1s
1us
1 Clock
Lg-
-SSC
-ppm error
0ppm
+ ppm error
+SSC
Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal
Maximum
9.949
9.999
10.024
10.025
10.026
10.051
10.101
ns
1,2,3
Notes
Definition
Units
Measurement
Window
Symbol
DIF 100
1 Clock
1us
0.1s
1us
1 Clock
Lg-
-SSC
-ppm error
0ppm
+ ppm error
+SSC
Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal
Maximum
DIF
100M
9.949
9.999
10.000
10.001
10.051
ns
1,2,3
1Guaranteed by desig n and characterization, not 100% tested in production.
3 Driven by PCIe output of main clock, PLL Mode or Bypass mode
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+ accuracy requirements. The
buffer itself does not contribute to ppm error.
Notes
Measurement
Window
Units
Symbol
Definition
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