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参数资料
| 型号： | 9FG1200DG-1LFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 0.240 INCH, 0.020 INCH PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件页数： | 21/23页 |
| 文件大小： | 188K |
| 代理商： | 9FG1200DG-1LFT |
IDT
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
02/08/10
ICS9FG1200D-1
7
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
3.3V Core Supply Voltage
VDD_A
GND - 0.5
VDD + 0.5V
V
1
3.3V Logic Supply Voltage
VDD_In
GND - 0.5
VDD + 0.5V
V
1
Storage Temperature
Ts
-65
150
°C
1
Ambient Operating Temp
Tambient
0
70
°C
1
Case Temperature
Tcase
115
°C
1
Input ESD protection
ESD prot
Human Body Model
2000
V
1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Input High Voltage
VIH
3.3 V +/-5%, except CLK_IN
2
VDD + 0.3
V
1
Input Low Voltage
VIL
3.3 V +/-5%, except CLK_IN
VSS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
Low Threshold Input-
High Voltage
VIH_FS
3.3 V +/-5%, Applies to
FS_A_410 pin
0.7
VDD + 0.3
V
1
Low Threshold Input-
Low Voltage
VIL_FS
3.3 V +/-5%, Applies to
FS_A_410 pin
VSS - 0.3
0.35
V
1
Operating Current
IDD3.3OP
all outputs driven
375
mA
1
Powerdown Current
IDD3.3PD
all differential pairs tri-stated
24
mA
1
Input Frequency
Fi
VDD = 3.3 V
100
400
MHz
3
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs
6
pF
1
COUT
Output pin capacitance
5
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_PD#
DIF output enable after
PD# de-assertion
300
us
1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
SMBus Voltage
VMAX
Maximum input voltage
5.5
V
1
Low-level Output Voltage
VOL
@ IPULLUP
0.4
V
1
Current sinking at
VOL = 0.4 V
IPULLUP
4mA
1
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
Input Capacitance
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