参数资料
型号: 9FG1200DG-1LFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 400 MHz, OTHER CLOCK GENERATOR, PDSO56
封装: 0.240 INCH, 0.020 INCH PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件页数: 6/23页
文件大小: 188K
代理商: 9FG1200DG-1LFT
IDT
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
02/08/10
ICS9FG1200D-1
14
SMBusTable: Output Enable Readback Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
R
X
Bit 6
R
X
Bit 5
R
X
Bit 4
R
X
Bit 3
R
X
Bit 2
R
X
Bit 1
R
X
Bit 0
R
X
SMBusTable: Vendor & Revision ID Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RID3
R
-
X
Bit 6
RID2
R
-
X
Bit 5
RID1
R
-
X
Bit 4
RID0
R
-
X
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
SMBusTable: DEVICE ID
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RW
1
Bit 6
RW
1
Bit 5
RW
0
Bit 4
RW
0
Bit 3
RW
0
Bit 2
RW
0
Bit 1
RW
0
Bit 0
RW
0
SMBusTable: Byte Count Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
BC7
RW
-
0
Bit 6
BC6
RW
-
0
Bit 5
BC5
RW
-
0
Bit 4
BC4
RW
-
0
Bit 3
BC3
RW
-
1
Bit 2
BC2
RW
-
0
Bit 1
BC1
RW
-
0
Bit 0
BC0
RW
-
1
Writing to this register
configures how many
bytes will be read back.
Reserved
Device ID 5
Reserved
Device ID 4
Reserved
Device ID 3
Reserved
Device ID 0
Byte 7
-
Byte 5
-
Readback - FS_A_410
Byte 4
Readback
46
Readback
Readback - HIGH_BW# In
-
VENDOR ID
-
1
30
53
44
41
Device ID 6
Byte 6
-
Readback - OE9# Input
REVISION ID
-
Device ID 7 (MSB)
Reserved
Readback - SMB_A2_PLLBYP# In
Readback
Reserved
Readback
Readback - OE8# Input
Readback
Reserved
Readback
Readback - OE10_11# Input
Readback
Reserved
Device ID 2
Reserved
Device ID 1
Reserved
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