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参数资料
型号： 9LPRS464YGLFT
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 时钟产生/分配
英文描述： 240 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153N, TSSOP-56
文件页数： 7/23页
文件大小： 246K
代理商： 9LPRS464YGLFT
15
ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
IDTTM/ICSTM
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
1377A—04/07/08
SMBus Table: Spread Spectrum Enable and CPU Frequency Select Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
FS Source
Latched Input or SMBus
Frequency Select
RW
Latched
Inputs
SMBus
0
Bit 6
-
ATIG SS_EN
ATIG Spread Spectrum Enable
RW
Disable
Enable
0
Bit 5
-
SRC SS_EN
SRC Spread Spectrum Enable
RW
Disable
Enable
0
Bit 4
-
CPU SS_EN
CPU Spread Spectrum Enable
RW
Disable
Enable
0
Bit 3
-
CPU FS3
CPU Freq Select Bit 3
RW
0
Bit 2
-
CPU FS2
CPU Freq Select Bit 2
RW
Latch
Bit 1
-
CPU FS1
CPU Freq Select Bit 1
RW
Latch
Bit 0
-
CPU FS0
CPU Freq Select Bit 0
RW
Latch
Note: Each Spread Spectrum Enable bit is independent from the other.
Bit(6:4) must all set to "1" in order to enable spread for CPU, SRC and ATIG clocks.
SMBus Table: Output Control Register
Byte 1
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
7
48MHz_1
48MHz_1 Output Enable
RW
Disable
Enable
1
Bit 6
6
48MHz_0
48MHz_0 Output Enable
RW
Disable
Enable
1
Bit 5
54
REF2
REF2 Output Enable
RW
Disable
Enable
1
Bit 4
55
REF1
REF1 Output Enable
RW
Disable
Enable
1
Bit 3
56
REF0
REF0 Output Enable
RW
Disable
Enable
1
Bit 2
51
HTTCLK0
HTTCLK0 Output Enable
RW
Disable
Enable
1
Bit 1
44,43
CPUCLK1
CPUCLK1 Output Enable
RW
Disable
Enable
1
Bit 0
48,47
CPUCLK0
CPUCLK0 Output Enable
RW
Disable
Enable
1
SMBus Table: ATIGCLK and CLKREQB# Output Control Register
Byte 2
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
31,30
ATIGCLK1
ATIGCLK1 Output Enable
RW
Disable
Enable
1
Bit 4
35,34
ATIGCLK0
ATIGCLK0 Output Enable
RW
Disable
Enable
1
Bit 3
20,21
REQBSRC2
CLKREQB# Controls SRC2
RW
Does not
control
Controls
0
Bit 2
0
Bit 1
24,25
REQBSRC1
CLKREQB# Controls SRC1
RW
Does not
control
Controls
0
Bit 0
0
SMBus Table: SRCCLK Output Control Register
Byte 3
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
12,13
SRCCLK5
RW
Disable
Enable
1
Bit 6
16,17
SRCCLK4
RW
Disable
Enable
1
Bit 5
18,19
SRCCLK3
RW
Disable
Enable
1
Bit 4
20,21
SRCCLK2
RW
Disable
Enable
1
Bit 3
Reserved
-
1
Bit 2
24,25
SRCCLK1
RW
Disable
Enable
1
Bit 1
Reserved
-
1
Bit 0
39,38
SRCCLK0
RW
Disable
Enable
1
See Table 1:
CPU Frequency Selection
Table
Master Output control. Enables
or disables output, regardless of
CLKREQ# inputs.
Reserved
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