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参数资料
| 型号： | 9LPRS502YFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件页数： | 15/29页 |
| 文件大小： | 279K |
| 代理商： | 9LPRS502YFLFT |
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IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
22
Byte 10 CK505 Rev 0.85 functions (ICS Rev H silicon and higher)
Bit
Pin
Name
Description
Type
Default
7
SRC5_EN Readback
Readback of SRC5 enable latch
R
Latch
6
Reserved
RW
0
5
Reserved
RW
0
4
Reserved
RW
0
3
Reserved
RW
0
2
Reserved
RW
0
1
CPU 1 Stop Enable
Enables control of CPU1 with CPU_STOP#
RW
1
0
CPU 0 Stop Enable
Enables control of CPU 0 with CPU_STOP#
RW
1
Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher)
Bit
Pin
Name
Description
Type
Default
7
Reserved
RW
0
6
Reserved
RW
0
5
Reserved
RW
0
4
Reserved
RW
0
3
CPU2_iAMT_EN
Enables CPU2(ITP) output in iAMT state (M1)
RW
0
2
CPU1_iAMT_EN
Enables CPU1 output in iAMT state (M1)
RW
1
PCIe-Gen2
PCIe-Gen2 status
R
0
CPU2 Stop Enable
Enables control of CPU2(ITP) with CPU_STOP#
RW
1
Byte 12 Byte Count Register
Bit
Pin
Name
Description
Type
Default
7
Reserved
RW
0
6
Reserved
RW
0
5
BC5
RW
0
4
BC4
RW
0
3
BC3
RW
1
2
BC2
RW
1
BC1
RW
0
BC0
RW
1
Byte 13 CK505 PLL1 M/N Programming Register
Bit
Pin
Name
Description
Type
Default
7
N Div8
N Divider 8
RW
X
6
N Div9
N Divider 9
RW
X
5
M Div5
RW
X
4
M Div4
RW
X
3
M Div3
RW
X
2
M Div2
RW
X
1
M Div1
RW
X
0
M Div0
RW
X
Byte 14 CK505 PLL1 M/N Programming Register
Bit
Pin
Name
Description
Type
Default
7
N Div7
RW
X
6
N Div6
RW
X
5
N Div5
RW
X
4
N Div4
RW
X
3
N Div3
RW
X
2
N Div2
RW
X
1
N Div1
RW
X
0
N Div0
RW
X
Reserved
-
01
-
01
-
Stoppable
01
Off in iAMT
non-Gen2
Free Running
TBD
Free running in iAMT
PCIe Gen2 compliant
TBD
Off in iAMT
Stoppable
01
TBD
Free Running
SRC5 Enabled
TBD
Stoppable
TBD
01
CPU/PCI Stop Enabled
The decimal representation of M and N Divider in Byte
13 and 14 will configure the VCO frequency. Default
at power up = latch-in or Byte 0 Rom table.
-
The decimal representation of M and N Divider in Byte
13 and 14 will configure the VCO frequency. Default
at power up = latch-in or Byte 0 Rom table.
Read Back byte count register,
max bytes = 32
Reserved
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9LPRS502YGLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR |
| 9LPRS502YKLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR |
| 9LPRS509HGLF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS509HGLF LOGIC AND TIMING MISC - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS509HGLF Logic and Timing Misc |
| 9LPRS509PGLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9LPRS509PGLFT | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK 制造商:Integrated Device Technology Inc 功能描述:64 TSSOP (LEAD FREE) - Tape and Reel |
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