- 您现在的位置：买卖IC网 > PDF目录25570 > 9LPRS502YFLFT (INTEGRATED DEVICE TECHNOLOGY INC) SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 PDF资料下载
参数资料
| 型号： | 9LPRS502YFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件页数： | 2/29页 |
| 文件大小： | 279K |
| 代理商： | 9LPRS502YFLFT |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
10
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
43
VDDSRC_IO
PWR
Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
44
CPUC2_ITP/SRCC8
OUT
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
45
CPUT2_ITP/SRCT8
OUT
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
46
NC
Not Connected
47
VDDCPU_IO
PWR
Power supply for CPU outputs. 1.05 to 3.3V +/-5%.
48
CPUC1_F
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
49
CPUT1_F
OUT
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
50
GNDCPU
PWR
Ground Pin for CPU Outputs
51
CPUC0
OUT
Complement clock of low power differential CPU clock pair.
52
CPUT0
OUT
True clock of low power differential CPU clock pair.
53
VDDCPU
PWR
Power Supply 3.3V nominal.
54
CK_PWRGD/PD#
IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
55
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer
to Test Clarification Table.
56
GNDREF
PWR
Ground pin for crystal oscillator circuit
相关PDF资料 |
PDF描述 |
|---|---|
| 9LPRS502YGLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 9LPRS502YKLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC56 |
| 9LPRS511EGLF | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64 |
| 9LPRS525AFLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 9LPRS535BFLF | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 9LPRS502YGLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR |
| 9LPRS502YKLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR |
| 9LPRS509HGLF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS509HGLF LOGIC AND TIMING MISC - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS509HGLF Logic and Timing Misc |
| 9LPRS509PGLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9LPRS509PGLFT | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK 制造商:Integrated Device Technology Inc 功能描述:64 TSSOP (LEAD FREE) - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。