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参数资料
| 型号： | 9LPRS535CGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件页数： | 10/17页 |
| 文件大小： | 216K |
| 代理商： | 9LPRS535CGLFT |
2
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
1461A—07/28/09
SSOP/TSSOP Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
PCI0/CR#_A
I/O
3.3V PCI clock output or CR#_A input. Default is PCI0. To configure this pin as CR#_A, the PCI output must first be disabled in
Byte 2, bit 0.
Byte 5, bit 7: 0 = PCI0 enabled (default), 1= CR#_A enabled.
Byte 5, bit 6: 0 = CR#_A controls SRC0 (default), 1= CR#_A# controls SRC2.
2
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
3
PCI4/SRC5_EN
I/O
3.3V PCI clock output / SRC5 enable strap. On powerup, the logic value on this pin determines if SRC5 or
CPU_STOP#/PCI_STOP# is enabled. The latched value controls the pin function as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
4
PCI_F5/ITP_EN
I/O
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On
powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
5
GNDPCI
PWR Ground pin for the PCI outputs
6
VDD48
PWR Power pin for the 48MHz output.3.3V
7
USB_48MHz/FSLA
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed
48MHz USB clock output. 3.3V.
8
GND48
PWR Ground pin for the 48MHz outputs
9
VDD96_IO
PWR Power pin for the DOT96 clocks, nominal 1.05V to 3.3V.
10
DOT96T_LPR/SRCT0_LPR
OUT
True clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRCT0. After
powerup, this pin function may be changed to DOT96T via SMBus Byte 1, bit 7 as follows:
0= SRC0T
1=DOT96T
11
DOT96C_LPR/SRCC0_LPR
OUT
Complementary clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is
SRC0C. After powerup, this pin function may be changed to DOT96C via SMBus Byte 1, bit 7 as follows:
0= SRC0C
1=DOT96C
12
GND
PWR Ground pin.
13
VDD
PWR Power supply, nominal 3.3V
14
SE1
OUT CK505 Singled Ended Output 1. 3.3V.
15
GND
PWR Ground pin.
16
SRCT2_LPR/SATAT_LPR
OUT
True clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
17
SRCC2_LPR/SATAC_LPR
OUT
Complementary clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor
to GND needed.
18
GNDSRC
PWR Ground pin for the SRC outputs
19
SRCT3_LPR/CR#_C
I/O
True clock of push-pull SRC output with int. 33ohm series resistor/CR#_C input. Disable SRC3 via Byte 4, bit 7, before using as
CR#_C.
Byte 5, bit 3: 0=SRC3 (default), 1=CR#_C.
Byte 5, bit 2: 0=CR#_C controls SRC0 (default), 1=CR#_C controls SRC2
20
SRCC3_LPR/CR#_D
I/O
Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_D input. Disable SRC3 via Byte 4, bit 7,
before using as CR#_D.
Byte 5, bit 1: 0=SRC3 (default),1=CR#_D.
Byte 5, bit 0: 0=CR#_D controls N/A (default), 1=CR#_D controls SRC4
21
VDDSRC_IO
PWR
1.05V to 3.3V from external power supply
22
SRCT4_LPR
OUT True clock of push-pull SRC output with int. 33ohm series resistor.
23
SRCC4_LPR
OUT Complementary clock of push-pull SRC output with int. 33ohm series resistor.
24
CPU_STOP#/SRCC5_LPR
I/O
Stops all CPUCLK, except those set to be free running clocks /
Complementary clock of push-pull SRC pair with int. 33ohm series resistor.
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