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参数资料
| 型号： | 9LPRS535CGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件页数： | 15/17页 |
| 文件大小： | 216K |
| 代理商： | 9LPRS535CGLFT |
7
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
1461A—07/28/09
Electrical Characteristics - USB48MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
2,4
Clock period
Tperiod
48.00MHz output nominal
20.83125
20.83542
ns
2,3
Absolute min/max period
Tabs
48.00MHz output nominal
20.48125
21.18542
ns
2
CLK High Time
THIGH
8.216563
11.15198
V
CLK Low time
TLOW
7.816563
10.95198
V
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.55
V
V OH @MIN = 1.0 V
-29
mA
VOH@MAX = 3.135 V
-23
mA
VOL @ MIN = 1.95 V
29
mA
VOL @ MAX = 0.4 V
27
mA
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
2
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
2
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
2
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
350
ps
2
Output Low Current
IOL
Output High Current
IOH
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS Notes
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
2, 4
Clock period
Tperiod
14.318MHz output nominal
69.82033
69.86224
ns
2, 3
Absolute min/max period
Tabs
14.318MHz output nominal
69.83400
70.84800
ns
2
CLK High Time
THIGH
29.97543
38.46654
V
CLK Low time
TLOW
29.57543
38.26654
V
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
Output High Current
IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
-33
mA
Output Low Current
IOL
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
30
38
mA
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
2
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
1000
ps
2
1Edge rate in system is measured from 0.8V to 2.0V.
2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V
3 The average period over any 1us period of time
NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz
Clock Jitter Specs - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
CPU Jitter - Cycle to Cycle
CPUJC2C
Differential Measurement
85
ps
1
SRC Jitter - Cycle to Cycle
SRCJC2C
Differential Measurement
125
ps
1,2
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential Measurement
250
ps
1
1JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system
performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece
2 Phase jitter requirement: The deisgnated Ge2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed on a
componnet test board under quiet condittions with all outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG or equivalent. Measurement
methodology is as defined by the PCI SIG.
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
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