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参数资料
| 型号： | 9UMS9001YKLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC14 |
| 封装： | ROHS COMPLIANT, PLASTIC, MLF-56 |
| 文件页数： | 8/15页 |
| 文件大小： | 113K |
| 代理商： | 9UMS9001YKLF-T |
IDTTM/ICSTM PC MAIN CLOCK - CK540
1247A—08/28/08
Advance Information
ICS9UMS9001
PC MAIN CLOCK - CK540
2
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
X2
OUT Crystal output, nominally 14.318MHz.
2
X1
IN
Crystal input, Nominally 14.318MHz.
3
VDDREFIO_3.3
PWR Power pin for the REF output and crystal oscillator. 3.3V nominal.
4
REF0
OUT 3.3V 14.318MHz reference clock
5
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
6
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
7TEST_SEL
IN
3.3V input that puts the part in test mode. This is a realtime input. See the Test Clarification Table for
details.
8
TEST_MODE
PWR When Test mode is selected, this chooses either hi-Z or REF/N for the outputs.
9
PCI_STOP#
IN
3.3V tolerant input that stops all PCI and SRC clocks, except those set to be free running.
10
VDDIO_PCI3.3
PWR 3.3V power supply for the PCI outputs
11
PCI0
OUT 3.3V PCI clock output.
12
PCI1
OUT 3.3V PCI clock output.
13
PCI_F2
OUT Free running 3.3V PCI clock output
14
GNDPCI
PWR Ground for PCI output clocks.
15
GND48
PWR Ground for the USB clock.
16
USB_48MHz
OUT
Fixed 3.3V 48MHz USB clock output
17
VDD48IO_3.3
PWR 3.3V Power supply for the 48MHz output
18
VDD48PLL_3.3
PWR 3.3V Power supply for the 48/96MHz PLL
19
VDDIO_96Mhz
PWR Power supply for DOT96 output. VDD_IO = 1.05 to 3.3V +/-5%.
20
DOT96C_LPRS
OUT
Complement side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external
series resistor required).
21
DOT96T_LPRS
PWR
True side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external series
resistor required).
22
GND
PWR Ground for 96MHz output
23
GND
OUT Ground for LCD 100 MHz output.
24
LCD100C_LPRS
OUT
Complement side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated
(No external series resistor required).
25
LCD100T_LPRS
OUT
True side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated (No
external series resistor required).
26
VDDIO_LCD
PWR Power supply for LCD100 output. VDD_IO = 1.05 to 3.3V +/-5%.
27
VDDLCDPLL_3.3
PWR 3.3V Power supply for the LCD100 Spreading PLL
28
CLKREQ1#
IN
Clock request input for SRC output pair 1. See the SRC, LCD, DOT Power Management Table for
details
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相关代理商/技术参数 |
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| 9UMS9610BKLF | 制造商:Integrated Device Technology Inc 功能描述:9UMS9610BKLF - Bulk |
| 9UMS9610CKLF | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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| 9UMS9633BFILF | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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