Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Output State Operation
The output state (VOUT pin) of this device switches to low (on)
when an incident magnetic field, perpendicular to the Hall ele-
ment, exceeds the operate point threshold, BOP. After turn-on,
the output voltage is VOUT(SAT) (see figure 2). When the magnetic
field is reduced below the release point, BRP, the device output
goes high (off), VOUT(HIGH). The difference in the magnetic oper-
ate and release points is the hysteresis, BHYS, of the device. This
built-in hysteresis allows clean switching of the output even in
the presence of external mechanical vibration and electrical noise.
Removal of the magnetic field leaves the device output latched
low (on) if the last crossed switchpoint is BOP, or latched high
(off) if the last crossed switchpoint is BRP.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) gives an indeterminate output state. The correct
state is attained after the first excursion beyond BOP or BRP .
Micro-power Operation
Micro-power operation of the device involves duty cycle control
achieved by:
powering all circuits in the chip and latching the device output
state at the end of awake state periods, and
turning off the bias current to most circuits in the chip and
maintaining the device output state through sleep state periods.
This is illustrated in figure 3. The awake state duration, tawake_x,
is common in all defined modes of operation. The sleep state
duration is set at a longer duration than the awake period in order
to conserve power. During the sleep state, current consumption
is insignificant (equal to IDD(DIS)), but the device output does not
switch in response to changing incident magnetic fields.
The device shows maximum current consumption, IDD(EN), dur-
ing the awake state and minimal current consumption, IDD(DIS),
during the sleep state. Average current, IDD(AV), for micro-power
operation is derived from following formula:
IDD(AV)
.
IDD(EN) × tawake_x + IDD(DIS) × tsleep_x
=
tperiod_x
Three micro-power control modes are available:
Normal Clock mode
External Clock mode
Dual Clock mode
Selection of clock mode is determined by the configuration of
the EXTERNAL_CLK pin and the DUAL_CLK pin, and applied
voltages as illustrated in figure 4 and table 1.
Normal Clock Mode
When both device clock pins are left
floating or are grounded, the internal timing circuitry activates
the device for tawake_norm and deactivates it for the remainder,
tsleep, of the duty cycle period, tperiod_norm. The short awake time
Figure 2. Device output switching logic
B
OP
B
RP
BHYS
VOUT(HIGH) (off)
V
OUT
VOUT(SAT)(on)
Switch
to
Low
Switch
to
High
B+
B–
0
V+
Figure 3. Micro-power behavior of the device
0
t
tperiod_x
tawake_x
tsleep_x
I
DD(EN)
I
DD
IDD(DIS)
Sample and
output latched